[riscv64][wasm-simd] Prototype relaxed integer Dot product instructions

Port commit a52b44f0

Original Commit Message:

    Prototype the instruction on the interpreter, and Arm64. Details of
    instruction lowerings on all relevant architectures can be found at:
    https://github.com/WebAssembly/relaxed-simd/issues/52

Change-Id: Ie0415f5c6a543517aa488a36ea5e575c6612ec0e
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3687424
Auto-Submit: Yahan Lu <yahan@iscas.ac.cn>
Commit-Queue: ji qiu <qiuji@iscas.ac.cn>
Reviewed-by: ji qiu <qiuji@iscas.ac.cn>
Cr-Commit-Position: refs/heads/main@{#80951}

src/wasm/baseline/riscv64/liftoff-assembler-riscv64.h

@@ -2174,6 +2174,19 @@ void LiftoffAssembler::emit_i16x8_relaxed_q15mulr_s(LiftoffRegister dst,
   vsmul_vv(dst.fp().toV(), src1.fp().toV(), src2.fp().toV());
 }
 
+void LiftoffAssembler::emit_i16x8_dot_i8x16_i7x16_s(LiftoffRegister dst,
+                                                    LiftoffRegister lhs,
+                                                    LiftoffRegister rhs) {
+  bailout(kSimd, "emit_i16x8_dot_i8x16_i7x16_s");
+}
+
+void LiftoffAssembler::emit_i32x4_dot_i8x16_i7x16_add_s(LiftoffRegister dst,
+                                                        LiftoffRegister lhs,
+                                                        LiftoffRegister rhs,
+                                                        LiftoffRegister acc) {
+  bailout(kSimd, "emit_i32x4_dot_i8x16_i7x16_add_s");
+}
+
 void LiftoffAssembler::emit_i64x2_bitmask(LiftoffRegister dst,
                                           LiftoffRegister src) {
   VU.set(kScratchReg, E64, m1);