s390: Implemented Atomic64 operations

Change-Id: I7591ccc55405a2fbd258bf28d53cd40a4bddf2c2
Reviewed-on: https://chromium-review.googlesource.com/1255102Reviewed-by: Junliang Yan <jyan@ca.ibm.com>
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Commit-Queue: Junliang Yan <jyan@ca.ibm.com>
Cr-Commit-Position: refs/heads/master@{#56344}

src/compiler/instruction-selector.cc

@@ -2427,7 +2427,8 @@ void InstructionSelector::VisitWord32AtomicPairCompareExchange(Node* node) {
 }
 #endif  // !V8_TARGET_ARCH_IA32 && !V8_TARGET_ARCH_ARM
 
-#if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_MIPS64
+#if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_MIPS64 && \
+    !V8_TARGET_ARCH_S390
 void InstructionSelector::VisitWord64AtomicLoad(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitWord64AtomicStore(Node* node) {
@@ -2451,7 +2452,8 @@ void InstructionSelector::VisitWord64AtomicExchange(Node* node) {
 void InstructionSelector::VisitWord64AtomicCompareExchange(Node* node) {
   UNIMPLEMENTED();
 }
-#endif  // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM64
+#endif  // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM64 &&
+        // !V8_TARGET_ARCH_MIPS64 && !V8_TARGET_ARCH_S390
 
 #if !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_MIPS && \
     !V8_TARGET_ARCH_MIPS64 && !V8_TARGET_ARCH_IA32

src/compiler/s390/instruction-scheduler-s390.cc

@@ -169,6 +169,46 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kS390_StackClaim:
       return kHasSideEffect;
 
+    case kS390_Word64AtomicLoadUint8:
+    case kS390_Word64AtomicLoadUint16:
+    case kS390_Word64AtomicLoadUint32:
+    case kS390_Word64AtomicLoadUint64:
+      return kIsLoadOperation;
+
+    case kS390_Word64AtomicStoreUint8:
+    case kS390_Word64AtomicStoreUint16:
+    case kS390_Word64AtomicStoreUint32:
+    case kS390_Word64AtomicStoreUint64:
+    case kS390_Word64AtomicExchangeUint8:
+    case kS390_Word64AtomicExchangeUint16:
+    case kS390_Word64AtomicExchangeUint32:
+    case kS390_Word64AtomicExchangeUint64:
+    case kS390_Word64AtomicCompareExchangeUint8:
+    case kS390_Word64AtomicCompareExchangeUint16:
+    case kS390_Word64AtomicCompareExchangeUint32:
+    case kS390_Word64AtomicCompareExchangeUint64:
+    case kS390_Word64AtomicAddUint8:
+    case kS390_Word64AtomicAddUint16:
+    case kS390_Word64AtomicAddUint32:
+    case kS390_Word64AtomicAddUint64:
+    case kS390_Word64AtomicSubUint8:
+    case kS390_Word64AtomicSubUint16:
+    case kS390_Word64AtomicSubUint32:
+    case kS390_Word64AtomicSubUint64:
+    case kS390_Word64AtomicAndUint8:
+    case kS390_Word64AtomicAndUint16:
+    case kS390_Word64AtomicAndUint32:
+    case kS390_Word64AtomicAndUint64:
+    case kS390_Word64AtomicOrUint8:
+    case kS390_Word64AtomicOrUint16:
+    case kS390_Word64AtomicOrUint32:
+    case kS390_Word64AtomicOrUint64:
+    case kS390_Word64AtomicXorUint8:
+    case kS390_Word64AtomicXorUint16:
+    case kS390_Word64AtomicXorUint32:
+    case kS390_Word64AtomicXorUint64:
+      return kHasSideEffect;
+
 #define CASE(Name) case k##Name:
       COMMON_ARCH_OPCODE_LIST(CASE)
 #undef CASE

src/s390/macro-assembler-s390.cc

@@ -2879,6 +2879,12 @@ void TurboAssembler::LoadAndSub32(Register dst, Register src,
   laa(dst, dst, opnd);
 }
 
+void TurboAssembler::LoadAndSub64(Register dst, Register src,
+                                  const MemOperand& opnd) {
+  lcgr(dst, src);
+  laag(dst, dst, opnd);
+}
+
 //----------------------------------------------------------------------------
 //  Subtract Logical Instructions
 //----------------------------------------------------------------------------
@@ -3369,6 +3375,12 @@ void TurboAssembler::CmpAndSwap(Register old_val, Register new_val,
   }
 }
 
+void TurboAssembler::CmpAndSwap64(Register old_val, Register new_val,
+                                  const MemOperand& opnd) {
+  DCHECK(is_int20(opnd.offset()));
+  csg(old_val, new_val, opnd);
+}
+
 //-----------------------------------------------------------------------------
 // Compare Logical Helpers
 //-----------------------------------------------------------------------------

src/s390/macro-assembler-s390.h

@@ -325,6 +325,7 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
   void SubP(Register dst, const MemOperand& opnd);
   void SubP_ExtendSrc(Register dst, const MemOperand& opnd);
   void LoadAndSub32(Register dst, Register src, const MemOperand& opnd);
+  void LoadAndSub64(Register dst, Register src, const MemOperand& opnd);
 
   // Subtract Logical (Register - Mem)
   void SubLogical(Register dst, const MemOperand& opnd);
@@ -392,6 +393,7 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
   void Cmp32(Register dst, const MemOperand& opnd);
   void CmpP(Register dst, const MemOperand& opnd);
   void CmpAndSwap(Register old_val, Register new_val, const MemOperand& opnd);
+  void CmpAndSwap64(Register old_val, Register new_val, const MemOperand& opnd);
 
   // Compare Logical
   void CmpLogical32(Register src1, Register src2);

src/s390/simulator-s390.cc

@@ -1369,6 +1369,7 @@ void Simulator::EvalTableInit() {
   EvalTable[SRLG] = &Simulator::Evaluate_SRLG;
   EvalTable[SLLG] = &Simulator::Evaluate_SLLG;
   EvalTable[CSY] = &Simulator::Evaluate_CSY;
+  EvalTable[CSG] = &Simulator::Evaluate_CSG;
   EvalTable[RLLG] = &Simulator::Evaluate_RLLG;
   EvalTable[RLL] = &Simulator::Evaluate_RLL;
   EvalTable[STMG] = &Simulator::Evaluate_STMG;
@@ -8778,9 +8779,26 @@ EVALUATE(CSY) {
 }
 
 EVALUATE(CSG) {
-  UNIMPLEMENTED();
-  USE(instr);
-  return 0;
+  DCHECK_OPCODE(CSG);
+  DECODE_RSY_A_INSTRUCTION(r1, r3, b2, d2);
+  int32_t offset = d2;
+  int64_t b2_val = (b2 == 0) ? 0 : get_register(b2);
+  intptr_t target_addr = static_cast<intptr_t>(b2_val) + offset;
+
+  int64_t r1_val = get_register(r1);
+  int64_t r3_val = get_register(r3);
+
+  DCHECK_EQ(target_addr & 0x3, 0);
+  bool is_success = __atomic_compare_exchange_n(
+      reinterpret_cast<int64_t*>(target_addr), &r1_val, r3_val, true,
+      __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST);
+  if (!is_success) {
+    set_register(r1, r1_val);
+    condition_reg_ = 0x4;
+  } else {
+    condition_reg_ = 0x8;
+  }
+  return length;
 }
 
 EVALUATE(RLLG) {
@@ -9153,28 +9171,38 @@ EVALUATE(STOCG) {
   return 0;
 }
 
+#define ATOMIC_LOAD_AND_UPDATE_WORD64(op)                             \
+  DECODE_RSY_A_INSTRUCTION(r1, r3, b2, d2);                           \
+  int64_t b2_val = (b2 == 0) ? 0 : get_register(b2);                  \
+  intptr_t addr = static_cast<intptr_t>(b2_val) + d2;                 \
+  int64_t r3_val = get_register(r3);                                  \
+  DCHECK_EQ(addr & 0x3, 0);                                           \
+  int64_t r1_val =                                                    \
+      op(reinterpret_cast<int64_t*>(addr), r3_val, __ATOMIC_SEQ_CST); \
+  set_register(r1, r1_val);
+
 EVALUATE(LANG) {
-  UNIMPLEMENTED();
-  USE(instr);
-  return 0;
+  DCHECK_OPCODE(LANG);
+  ATOMIC_LOAD_AND_UPDATE_WORD64(__atomic_fetch_and);
+  return length;
 }
 
 EVALUATE(LAOG) {
-  UNIMPLEMENTED();
-  USE(instr);
-  return 0;
+  DCHECK_OPCODE(LAOG);
+  ATOMIC_LOAD_AND_UPDATE_WORD64(__atomic_fetch_or);
+  return length;
 }
 
 EVALUATE(LAXG) {
-  UNIMPLEMENTED();
-  USE(instr);
-  return 0;
+  DCHECK_OPCODE(LAXG);
+  ATOMIC_LOAD_AND_UPDATE_WORD64(__atomic_fetch_xor);
+  return length;
 }
 
 EVALUATE(LAAG) {
-  UNIMPLEMENTED();
-  USE(instr);
-  return 0;
+  DCHECK_OPCODE(LAAG);
+  ATOMIC_LOAD_AND_UPDATE_WORD64(__atomic_fetch_add);
+  return length;
 }
 
 EVALUATE(LAALG) {
@@ -9183,6 +9211,8 @@ EVALUATE(LAALG) {
   return 0;
 }
 
+#undef ATOMIC_LOAD_AND_UPDATE_WORD64
+
 EVALUATE(LOC) {
   UNIMPLEMENTED();
   USE(instr);