[wasm-simd] Merge ARM64 any true opcodes

We are hitting some limits in number of opcodes on ARM64. Try to reduce
it by merging AnyTrue opcodes (from 4 to 1) since the codegen is
identical.

Bug: v8:10930
Change-Id: Ib0bcedbd24d122a4da1ffcb29c1e4b5656fa6ac2
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2422087Reviewed-by: Bill Budge <bbudge@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#70063}

src/compiler/backend/arm64/code-generator-arm64.cc

@@ -2657,13 +2657,10 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
     __ Cset(i.OutputRegister32(), ne);                     \
     break;                                                 \
   }
-      // for AnyTrue, the format does not matter, umaxv does not support 2D
-      SIMD_REDUCE_OP_CASE(kArm64V64x2AnyTrue, Umaxv, kFormatS, 4S);
-      SIMD_REDUCE_OP_CASE(kArm64V32x4AnyTrue, Umaxv, kFormatS, 4S);
+      // For AnyTrue, the format does not matter.
+      SIMD_REDUCE_OP_CASE(kArm64V128AnyTrue, Umaxv, kFormatS, 4S);
       SIMD_REDUCE_OP_CASE(kArm64V32x4AllTrue, Uminv, kFormatS, 4S);
-      SIMD_REDUCE_OP_CASE(kArm64V16x8AnyTrue, Umaxv, kFormatH, 8H);
       SIMD_REDUCE_OP_CASE(kArm64V16x8AllTrue, Uminv, kFormatH, 8H);
-      SIMD_REDUCE_OP_CASE(kArm64V8x16AnyTrue, Umaxv, kFormatB, 16B);
       SIMD_REDUCE_OP_CASE(kArm64V8x16AllTrue, Uminv, kFormatB, 16B);
   }
   return kSuccess;

src/compiler/backend/arm64/instruction-codes-arm64.h

@@ -375,13 +375,10 @@ namespace compiler {
   V(Arm64S8x8Reverse)                       \
   V(Arm64S8x4Reverse)                       \
   V(Arm64S8x2Reverse)                       \
-  V(Arm64V64x2AnyTrue)                      \
+  V(Arm64V128AnyTrue)                       \
   V(Arm64V64x2AllTrue)                      \
-  V(Arm64V32x4AnyTrue)                      \
   V(Arm64V32x4AllTrue)                      \
-  V(Arm64V16x8AnyTrue)                      \
   V(Arm64V16x8AllTrue)                      \
-  V(Arm64V8x16AnyTrue)                      \
   V(Arm64V8x16AllTrue)                      \
   V(Arm64S8x16LoadSplat)                    \
   V(Arm64S16x8LoadSplat)                    \

src/compiler/backend/arm64/instruction-scheduler-arm64.cc

@@ -345,13 +345,10 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kArm64S8x8Reverse:
     case kArm64S8x4Reverse:
     case kArm64S8x2Reverse:
-    case kArm64V64x2AnyTrue:
+    case kArm64V128AnyTrue:
     case kArm64V64x2AllTrue:
-    case kArm64V32x4AnyTrue:
     case kArm64V32x4AllTrue:
-    case kArm64V16x8AnyTrue:
     case kArm64V16x8AllTrue:
-    case kArm64V8x16AnyTrue:
     case kArm64V8x16AllTrue:
     case kArm64TestAndBranch32:
     case kArm64TestAndBranch:

src/compiler/backend/arm64/instruction-selector-arm64.cc

@@ -3229,13 +3229,13 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(I8x16Neg, kArm64I8x16Neg)                             \
   V(I8x16Abs, kArm64I8x16Abs)                             \
   V(S128Not, kArm64S128Not)                               \
-  V(V64x2AnyTrue, kArm64V64x2AnyTrue)                     \
+  V(V64x2AnyTrue, kArm64V128AnyTrue)                      \
   V(V64x2AllTrue, kArm64V64x2AllTrue)                     \
-  V(V32x4AnyTrue, kArm64V32x4AnyTrue)                     \
+  V(V32x4AnyTrue, kArm64V128AnyTrue)                      \
   V(V32x4AllTrue, kArm64V32x4AllTrue)                     \
-  V(V16x8AnyTrue, kArm64V16x8AnyTrue)                     \
+  V(V16x8AnyTrue, kArm64V128AnyTrue)                      \
   V(V16x8AllTrue, kArm64V16x8AllTrue)                     \
-  V(V8x16AnyTrue, kArm64V8x16AnyTrue)                     \
+  V(V8x16AnyTrue, kArm64V128AnyTrue)                      \
   V(V8x16AllTrue, kArm64V8x16AllTrue)
 
 #define SIMD_SHIFT_OP_LIST(V) \