Commit 2cda9fc6 authored by Milad Fa's avatar Milad Fa Committed by V8 LUCI CQ

PPC [liftoff]: Implement simd 8x16 population count

Drive-by: dtype and stype are removed from SIMD_UNOP_LIST,
toSimd() requires them to all be of type `fp`.

Change-Id: Ifdfe187e2b143fb8fa785c44344bea38ea7e10f8
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3916553
Commit-Queue: Milad Farazmand <mfarazma@redhat.com>
Reviewed-by: 's avatarJunliang Yan <junyan@redhat.com>
Cr-Commit-Position: refs/heads/main@{#83431}
parent 4993fc12
......@@ -3779,7 +3779,8 @@ SIMD_SHIFT_LIST(EMIT_SIMD_SHIFT)
V(F32x4Floor, xvrspim) \
V(F32x4Trunc, xvrspiz) \
V(I64x2Neg, vnegd) \
V(I32x4Neg, vnegw)
V(I32x4Neg, vnegw) \
V(I8x16Popcnt, vpopcntb)
#define EMIT_SIMD_UNOP(name, op) \
void TurboAssembler::name(Simd128Register dst, Simd128Register src) { \
......
......@@ -1174,7 +1174,8 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
V(F32x4Floor) \
V(F32x4Trunc) \
V(I64x2Neg) \
V(I32x4Neg)
V(I32x4Neg) \
V(I8x16Popcnt)
#define PROTOTYPE_SIMD_UNOP(name) \
void name(Simd128Register dst, Simd128Register src);
......
......@@ -2293,7 +2293,8 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
V(F32x4Sqrt) \
V(F32x4Ceil) \
V(F32x4Floor) \
V(F32x4Trunc)
V(F32x4Trunc) \
V(I8x16Popcnt)
#define EMIT_SIMD_UNOP(name) \
case kPPC_##name: { \
......@@ -3362,10 +3363,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ vinsertd(dst, kScratchSimd128Reg, Operand(lane_number));
break;
}
case kPPC_I8x16Popcnt: {
__ vpopcntb(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kPPC_StoreCompressTagged: {
size_t index = 0;
AddressingMode mode = kMode_None;
......
......@@ -1876,27 +1876,28 @@ SIMD_SHIFT_RI_LIST(EMIT_SIMD_SHIFT_RI)
#undef EMIT_SIMD_SHIFT_RI
#undef SIMD_SHIFT_RI_LIST
#define SIMD_UNOP_LIST(V) \
V(f64x2_abs, F64x2Abs, fp, fp, , void) \
V(f64x2_neg, F64x2Neg, fp, fp, , void) \
V(f64x2_sqrt, F64x2Sqrt, fp, fp, , void) \
V(f64x2_ceil, F64x2Ceil, fp, fp, true, bool) \
V(f64x2_floor, F64x2Floor, fp, fp, true, bool) \
V(f64x2_trunc, F64x2Trunc, fp, fp, true, bool) \
V(f32x4_abs, F32x4Abs, fp, fp, , void) \
V(f32x4_neg, F32x4Neg, fp, fp, , void) \
V(i64x2_neg, I64x2Neg, fp, fp, , void) \
V(i32x4_neg, I32x4Neg, fp, fp, , void) \
V(f32x4_sqrt, F32x4Sqrt, fp, fp, , void) \
V(f32x4_ceil, F32x4Ceil, fp, fp, true, bool) \
V(f32x4_floor, F32x4Floor, fp, fp, true, bool) \
V(f32x4_trunc, F32x4Trunc, fp, fp, true, bool)
#define EMIT_SIMD_UNOP(name, op, dtype, stype, return_val, return_type) \
return_type LiftoffAssembler::emit_##name(LiftoffRegister dst, \
LiftoffRegister src) { \
op(dst.dtype().toSimd(), src.stype().toSimd()); \
return return_val; \
#define SIMD_UNOP_LIST(V) \
V(f64x2_abs, F64x2Abs, , void) \
V(f64x2_neg, F64x2Neg, , void) \
V(f64x2_sqrt, F64x2Sqrt, , void) \
V(f64x2_ceil, F64x2Ceil, true, bool) \
V(f64x2_floor, F64x2Floor, true, bool) \
V(f64x2_trunc, F64x2Trunc, true, bool) \
V(f32x4_abs, F32x4Abs, , void) \
V(f32x4_neg, F32x4Neg, , void) \
V(i64x2_neg, I64x2Neg, , void) \
V(i32x4_neg, I32x4Neg, , void) \
V(f32x4_sqrt, F32x4Sqrt, , void) \
V(f32x4_ceil, F32x4Ceil, true, bool) \
V(f32x4_floor, F32x4Floor, true, bool) \
V(f32x4_trunc, F32x4Trunc, true, bool) \
V(i8x16_popcnt, I8x16Popcnt, , void)
#define EMIT_SIMD_UNOP(name, op, return_val, return_type) \
return_type LiftoffAssembler::emit_##name(LiftoffRegister dst, \
LiftoffRegister src) { \
op(dst.fp().toSimd(), src.fp().toSimd()); \
return return_val; \
}
SIMD_UNOP_LIST(EMIT_SIMD_UNOP)
#undef EMIT_SIMD_UNOP
......@@ -2504,11 +2505,6 @@ void LiftoffAssembler::emit_i8x16_shuffle(LiftoffRegister dst,
bailout(kSimd, "i8x16_shuffle");
}
void LiftoffAssembler::emit_i8x16_popcnt(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "i8x16.popcnt");
}
void LiftoffAssembler::emit_v128_anytrue(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "v8x16_anytrue");
......
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