Commit 1202e08e authored by jing.bao's avatar jing.bao Committed by Commit Bot

[wasm]implement simd lowering for F32x4AddHoriz and I16x8AddHoriz.

Change lowering for Store to use input replacement type.

Change-Id: Ic1fbbb37a3cc938fca7015d838933284bae6068e
Reviewed-on: https://chromium-review.googlesource.com/903266
Commit-Queue: Jing Bao <jing.bao@intel.com>
Reviewed-by: 's avatarAseem Garg <aseemgarg@chromium.org>
Cr-Commit-Position: refs/heads/master@{#51540}
parent 03f203bd
...@@ -117,6 +117,7 @@ void SimdScalarLowering::LowerGraph() { ...@@ -117,6 +117,7 @@ void SimdScalarLowering::LowerGraph() {
V(F32x4Abs) \ V(F32x4Abs) \
V(F32x4Neg) \ V(F32x4Neg) \
V(F32x4Add) \ V(F32x4Add) \
V(F32x4AddHoriz) \
V(F32x4Sub) \ V(F32x4Sub) \
V(F32x4Mul) \ V(F32x4Mul) \
V(F32x4Min) \ V(F32x4Min) \
...@@ -139,6 +140,7 @@ void SimdScalarLowering::LowerGraph() { ...@@ -139,6 +140,7 @@ void SimdScalarLowering::LowerGraph() {
V(I16x8ShrS) \ V(I16x8ShrS) \
V(I16x8Add) \ V(I16x8Add) \
V(I16x8AddSaturateS) \ V(I16x8AddSaturateS) \
V(I16x8AddHoriz) \
V(I16x8Sub) \ V(I16x8Sub) \
V(I16x8SubSaturateS) \ V(I16x8SubSaturateS) \
V(I16x8Mul) \ V(I16x8Mul) \
...@@ -355,7 +357,6 @@ void SimdScalarLowering::LowerStoreOp(MachineRepresentation rep, Node* node, ...@@ -355,7 +357,6 @@ void SimdScalarLowering::LowerStoreOp(MachineRepresentation rep, Node* node,
int num_lanes = NumLanes(rep_type); int num_lanes = NumLanes(rep_type);
Node** indices = zone()->NewArray<Node*>(num_lanes); Node** indices = zone()->NewArray<Node*>(num_lanes);
GetIndexNodes(index, indices, rep_type); GetIndexNodes(index, indices, rep_type);
DCHECK_LT(2, node->InputCount());
Node* value = node->InputAt(2); Node* value = node->InputAt(2);
DCHECK(HasReplacement(1, value)); DCHECK(HasReplacement(1, value));
Node** rep_nodes = zone()->NewArray<Node*>(num_lanes); Node** rep_nodes = zone()->NewArray<Node*>(num_lanes);
...@@ -453,7 +454,8 @@ Node* SimdScalarLowering::FixUpperBits(Node* input, int32_t shift) { ...@@ -453,7 +454,8 @@ Node* SimdScalarLowering::FixUpperBits(Node* input, int32_t shift) {
void SimdScalarLowering::LowerBinaryOpForSmallInt(Node* node, void SimdScalarLowering::LowerBinaryOpForSmallInt(Node* node,
SimdType input_rep_type, SimdType input_rep_type,
const Operator* op) { const Operator* op,
bool not_horizontal) {
DCHECK_EQ(2, node->InputCount()); DCHECK_EQ(2, node->InputCount());
DCHECK(input_rep_type == SimdType::kInt16x8 || DCHECK(input_rep_type == SimdType::kInt16x8 ||
input_rep_type == SimdType::kInt8x16); input_rep_type == SimdType::kInt8x16);
...@@ -463,9 +465,29 @@ void SimdScalarLowering::LowerBinaryOpForSmallInt(Node* node, ...@@ -463,9 +465,29 @@ void SimdScalarLowering::LowerBinaryOpForSmallInt(Node* node,
Node** rep_node = zone()->NewArray<Node*>(num_lanes); Node** rep_node = zone()->NewArray<Node*>(num_lanes);
int32_t shift_val = int32_t shift_val =
(input_rep_type == SimdType::kInt16x8) ? kShift16 : kShift8; (input_rep_type == SimdType::kInt16x8) ? kShift16 : kShift8;
for (int i = 0; i < num_lanes; ++i) { if (not_horizontal) {
rep_node[i] = FixUpperBits(graph()->NewNode(op, rep_left[i], rep_right[i]), for (int i = 0; i < num_lanes; ++i) {
shift_val); rep_node[i] = FixUpperBits(
graph()->NewNode(op, rep_left[i], rep_right[i]), shift_val);
}
} else {
for (int i = 0; i < num_lanes / 2; ++i) {
#if defined(V8_TARGET_BIG_ENDIAN)
rep_node[i] = FixUpperBits(
graph()->NewNode(op, rep_right[i * 2], rep_right[i * 2 + 1]),
shift_val);
rep_node[i + num_lanes / 2] = FixUpperBits(
graph()->NewNode(op, rep_left[i * 2], rep_left[i * 2 + 1]),
shift_val);
#else
rep_node[i] = FixUpperBits(
graph()->NewNode(op, rep_left[i * 2], rep_left[i * 2 + 1]),
shift_val);
rep_node[i + num_lanes / 2] = FixUpperBits(
graph()->NewNode(op, rep_right[i * 2], rep_right[i * 2 + 1]),
shift_val);
#endif
}
} }
ReplaceNode(node, rep_node, num_lanes); ReplaceNode(node, rep_node, num_lanes);
} }
...@@ -769,22 +791,35 @@ void SimdScalarLowering::LowerNode(Node* node) { ...@@ -769,22 +791,35 @@ void SimdScalarLowering::LowerNode(Node* node) {
break; break;
} }
case IrOpcode::kStore: { case IrOpcode::kStore: {
// For store operation, use replacement type of its input instead of the
// one of its effected node.
DCHECK_LT(2, node->InputCount());
SimdType input_rep_type = ReplacementType(node->InputAt(2));
if (input_rep_type != rep_type)
replacements_[node->id()].type = input_rep_type;
MachineRepresentation rep = MachineRepresentation rep =
StoreRepresentationOf(node->op()).representation(); StoreRepresentationOf(node->op()).representation();
WriteBarrierKind write_barrier_kind = WriteBarrierKind write_barrier_kind =
StoreRepresentationOf(node->op()).write_barrier_kind(); StoreRepresentationOf(node->op()).write_barrier_kind();
const Operator* store_op; const Operator* store_op;
store_op = machine()->Store(StoreRepresentation( store_op = machine()->Store(
MachineTypeFrom(rep_type).representation(), write_barrier_kind)); StoreRepresentation(MachineTypeFrom(input_rep_type).representation(),
LowerStoreOp(rep, node, store_op, rep_type); write_barrier_kind));
LowerStoreOp(rep, node, store_op, input_rep_type);
break; break;
} }
case IrOpcode::kUnalignedStore: { case IrOpcode::kUnalignedStore: {
// For store operation, use replacement type of its input instead of the
// one of its effected node.
DCHECK_LT(2, node->InputCount());
SimdType input_rep_type = ReplacementType(node->InputAt(2));
if (input_rep_type != rep_type)
replacements_[node->id()].type = input_rep_type;
MachineRepresentation rep = UnalignedStoreRepresentationOf(node->op()); MachineRepresentation rep = UnalignedStoreRepresentationOf(node->op());
const Operator* store_op; const Operator* store_op;
store_op = store_op = machine()->UnalignedStore(
machine()->UnalignedStore(MachineTypeFrom(rep_type).representation()); MachineTypeFrom(input_rep_type).representation());
LowerStoreOp(rep, node, store_op, rep_type); LowerStoreOp(rep, node, store_op, input_rep_type);
break; break;
} }
case IrOpcode::kReturn: { case IrOpcode::kReturn: {
...@@ -853,6 +888,10 @@ void SimdScalarLowering::LowerNode(Node* node) { ...@@ -853,6 +888,10 @@ void SimdScalarLowering::LowerNode(Node* node) {
LowerBinaryOp(node, rep_type, machine()->Int32Add(), false); LowerBinaryOp(node, rep_type, machine()->Int32Add(), false);
break; break;
} }
case IrOpcode::kI16x8AddHoriz: {
LowerBinaryOpForSmallInt(node, rep_type, machine()->Int32Add(), false);
break;
}
case IrOpcode::kI16x8Add: case IrOpcode::kI16x8Add:
case IrOpcode::kI8x16Add: { case IrOpcode::kI8x16Add: {
LowerBinaryOpForSmallInt(node, rep_type, machine()->Int32Add()); LowerBinaryOpForSmallInt(node, rep_type, machine()->Int32Add());
...@@ -962,6 +1001,10 @@ void SimdScalarLowering::LowerNode(Node* node) { ...@@ -962,6 +1001,10 @@ void SimdScalarLowering::LowerNode(Node* node) {
LowerShiftOp(node, rep_type); LowerShiftOp(node, rep_type);
break; break;
} }
case IrOpcode::kF32x4AddHoriz: {
LowerBinaryOp(node, rep_type, machine()->Float32Add(), false);
break;
}
#define F32X4_BINOP_CASE(name) \ #define F32X4_BINOP_CASE(name) \
case IrOpcode::kF32x4##name: { \ case IrOpcode::kF32x4##name: { \
LowerBinaryOp(node, rep_type, machine()->Float32##name()); \ LowerBinaryOp(node, rep_type, machine()->Float32##name()); \
......
...@@ -79,7 +79,7 @@ class SimdScalarLowering { ...@@ -79,7 +79,7 @@ class SimdScalarLowering {
bool invert_inputs = false); bool invert_inputs = false);
Node* FixUpperBits(Node* input, int32_t shift); Node* FixUpperBits(Node* input, int32_t shift);
void LowerBinaryOpForSmallInt(Node* node, SimdType input_rep_type, void LowerBinaryOpForSmallInt(Node* node, SimdType input_rep_type,
const Operator* op); const Operator* op, bool not_horizontal = true);
Node* Mask(Node* input, int32_t mask); Node* Mask(Node* input, int32_t mask);
void LowerSaturateBinaryOp(Node* node, SimdType input_rep_type, void LowerSaturateBinaryOp(Node* node, SimdType input_rep_type,
const Operator* op, bool is_signed); const Operator* op, bool is_signed);
......
...@@ -1613,12 +1613,12 @@ WASM_SIMD_TEST(I32x4AddHoriz) { ...@@ -1613,12 +1613,12 @@ WASM_SIMD_TEST(I32x4AddHoriz) {
RunBinaryLaneOpTest<int32_t>(lower_simd, kExprI32x4AddHoriz, {{1, 5, 9, 13}}); RunBinaryLaneOpTest<int32_t>(lower_simd, kExprI32x4AddHoriz, {{1, 5, 9, 13}});
} }
WASM_SIMD_COMPILED_TEST(I16x8AddHoriz) { WASM_SIMD_TEST(I16x8AddHoriz) {
RunBinaryLaneOpTest<int16_t>(lower_simd, kExprI16x8AddHoriz, RunBinaryLaneOpTest<int16_t>(lower_simd, kExprI16x8AddHoriz,
{{1, 5, 9, 13, 17, 21, 25, 29}}); {{1, 5, 9, 13, 17, 21, 25, 29}});
} }
WASM_SIMD_COMPILED_TEST(F32x4AddHoriz) { WASM_SIMD_TEST(F32x4AddHoriz) {
RunBinaryLaneOpTest<float>(lower_simd, kExprF32x4AddHoriz, RunBinaryLaneOpTest<float>(lower_simd, kExprF32x4AddHoriz,
{{1.0f, 5.0f, 9.0f, 13.0f}}); {{1.0f, 5.0f, 9.0f, 13.0f}});
} }
......
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