[Turbofan] Add more integer SIMD operations for ARM.

- Adds logical and arithmetic shifts for all integer types.
- Adds min and max for all integer types.
- Adds saturating add and subtract for small integer types.
- Removes lane operations from the MachineOperatorCache.

LOG=N
BUG=v8:4124

Review-Url: https://codereview.chromium.org/2668013003
Cr-Commit-Position: refs/heads/master@{#43005}

src/compiler/arm/code-generator-arm.cc

@@ -1582,6 +1582,16 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ vneg(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0));
       break;
     }
+    case kArmInt32x4ShiftLeftByScalar: {
+      __ vshl(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0),
+              i.InputInt5(1));
+      break;
+    }
+    case kArmInt32x4ShiftRightByScalar: {
+      __ vshr(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0),
+              i.InputInt5(1));
+      break;
+    }
     case kArmInt32x4Add: {
       __ vadd(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0),
               i.InputSimd128Register(1));
@@ -1630,6 +1640,21 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
               i.InputSimd128Register(1));
       break;
     }
+    case kArmUint32x4ShiftRightByScalar: {
+      __ vshr(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(0),
+              i.InputInt5(1));
+      break;
+    }
+    case kArmUint32x4Min: {
+      __ vmin(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(0),
+              i.InputSimd128Register(1));
+      break;
+    }
+    case kArmUint32x4Max: {
+      __ vmax(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(0),
+              i.InputSimd128Register(1));
+      break;
+    }
     case kArmUint32x4GreaterThan: {
       __ vcgt(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(0),
               i.InputSimd128Register(1));
@@ -1668,16 +1693,36 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ vneg(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0));
       break;
     }
+    case kArmInt16x8ShiftLeftByScalar: {
+      __ vshl(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0),
+              i.InputInt4(1));
+      break;
+    }
+    case kArmInt16x8ShiftRightByScalar: {
+      __ vshr(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0),
+              i.InputInt4(1));
+      break;
+    }
     case kArmInt16x8Add: {
       __ vadd(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0),
               i.InputSimd128Register(1));
       break;
     }
+    case kArmInt16x8AddSaturate: {
+      __ vqadd(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0),
+               i.InputSimd128Register(1));
+      break;
+    }
     case kArmInt16x8Sub: {
       __ vsub(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0),
               i.InputSimd128Register(1));
       break;
     }
+    case kArmInt16x8SubSaturate: {
+      __ vqsub(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0),
+               i.InputSimd128Register(1));
+      break;
+    }
     case kArmInt16x8Mul: {
       __ vmul(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0),
               i.InputSimd128Register(1));
@@ -1716,6 +1761,31 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
               i.InputSimd128Register(1));
       break;
     }
+    case kArmUint16x8ShiftRightByScalar: {
+      __ vshr(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0),
+              i.InputInt4(1));
+      break;
+    }
+    case kArmUint16x8AddSaturate: {
+      __ vqadd(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0),
+               i.InputSimd128Register(1));
+      break;
+    }
+    case kArmUint16x8SubSaturate: {
+      __ vqsub(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0),
+               i.InputSimd128Register(1));
+      break;
+    }
+    case kArmUint16x8Min: {
+      __ vmin(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0),
+              i.InputSimd128Register(1));
+      break;
+    }
+    case kArmUint16x8Max: {
+      __ vmax(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0),
+              i.InputSimd128Register(1));
+      break;
+    }
     case kArmUint16x8GreaterThan: {
       __ vcgt(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0),
               i.InputSimd128Register(1));
@@ -1745,16 +1815,36 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ vneg(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0));
       break;
     }
+    case kArmInt8x16ShiftLeftByScalar: {
+      __ vshl(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0),
+              i.InputInt3(1));
+      break;
+    }
+    case kArmInt8x16ShiftRightByScalar: {
+      __ vshr(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0),
+              i.InputInt3(1));
+      break;
+    }
     case kArmInt8x16Add: {
       __ vadd(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0),
               i.InputSimd128Register(1));
       break;
     }
+    case kArmInt8x16AddSaturate: {
+      __ vqadd(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0),
+               i.InputSimd128Register(1));
+      break;
+    }
     case kArmInt8x16Sub: {
       __ vsub(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0),
               i.InputSimd128Register(1));
       break;
     }
+    case kArmInt8x16SubSaturate: {
+      __ vqsub(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0),
+               i.InputSimd128Register(1));
+      break;
+    }
     case kArmInt8x16Mul: {
       __ vmul(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0),
               i.InputSimd128Register(1));
@@ -1792,6 +1882,31 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
               i.InputSimd128Register(1));
       break;
     }
+    case kArmUint8x16ShiftRightByScalar: {
+      __ vshr(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0),
+              i.InputInt3(1));
+      break;
+    }
+    case kArmUint8x16AddSaturate: {
+      __ vqadd(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0),
+               i.InputSimd128Register(1));
+      break;
+    }
+    case kArmUint8x16SubSaturate: {
+      __ vqsub(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0),
+               i.InputSimd128Register(1));
+      break;
+    }
+    case kArmUint8x16Min: {
+      __ vmin(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0),
+              i.InputSimd128Register(1));
+      break;
+    }
+    case kArmUint8x16Max: {
+      __ vmax(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0),
+              i.InputSimd128Register(1));
+      break;
+    }
     case kArmUint8x16GreaterThan: {
       __ vcgt(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0),
               i.InputSimd128Register(1));

src/compiler/arm/instruction-codes-arm.h

@@ -137,6 +137,8 @@ namespace compiler {
   V(ArmInt32x4FromFloat32x4)       \
   V(ArmUint32x4FromFloat32x4)      \
   V(ArmInt32x4Neg)                 \
+  V(ArmInt32x4ShiftLeftByScalar)   \
+  V(ArmInt32x4ShiftRightByScalar)  \
   V(ArmInt32x4Add)                 \
   V(ArmInt32x4Sub)                 \
   V(ArmInt32x4Mul)                 \
@@ -146,6 +148,9 @@ namespace compiler {
   V(ArmInt32x4NotEqual)            \
   V(ArmInt32x4GreaterThan)         \
   V(ArmInt32x4GreaterThanOrEqual)  \
+  V(ArmUint32x4ShiftRightByScalar) \
+  V(ArmUint32x4Min)                \
+  V(ArmUint32x4Max)                \
   V(ArmUint32x4GreaterThan)        \
   V(ArmUint32x4GreaterThanOrEqual) \
   V(ArmSimd32x4Select)             \
@@ -153,8 +158,12 @@ namespace compiler {
   V(ArmInt16x8ExtractLane)         \
   V(ArmInt16x8ReplaceLane)         \
   V(ArmInt16x8Neg)                 \
+  V(ArmInt16x8ShiftLeftByScalar)   \
+  V(ArmInt16x8ShiftRightByScalar)  \
   V(ArmInt16x8Add)                 \
+  V(ArmInt16x8AddSaturate)         \
   V(ArmInt16x8Sub)                 \
+  V(ArmInt16x8SubSaturate)         \
   V(ArmInt16x8Mul)                 \
   V(ArmInt16x8Min)                 \
   V(ArmInt16x8Max)                 \
@@ -162,14 +171,23 @@ namespace compiler {
   V(ArmInt16x8NotEqual)            \
   V(ArmInt16x8GreaterThan)         \
   V(ArmInt16x8GreaterThanOrEqual)  \
+  V(ArmUint16x8ShiftRightByScalar) \
+  V(ArmUint16x8AddSaturate)        \
+  V(ArmUint16x8SubSaturate)        \
+  V(ArmUint16x8Min)                \
+  V(ArmUint16x8Max)                \
   V(ArmUint16x8GreaterThan)        \
   V(ArmUint16x8GreaterThanOrEqual) \
   V(ArmInt8x16Splat)               \
   V(ArmInt8x16ExtractLane)         \
   V(ArmInt8x16ReplaceLane)         \
   V(ArmInt8x16Neg)                 \
+  V(ArmInt8x16ShiftLeftByScalar)   \
+  V(ArmInt8x16ShiftRightByScalar)  \
   V(ArmInt8x16Add)                 \
+  V(ArmInt8x16AddSaturate)         \
   V(ArmInt8x16Sub)                 \
+  V(ArmInt8x16SubSaturate)         \
   V(ArmInt8x16Mul)                 \
   V(ArmInt8x16Min)                 \
   V(ArmInt8x16Max)                 \
@@ -177,6 +195,11 @@ namespace compiler {
   V(ArmInt8x16NotEqual)            \
   V(ArmInt8x16GreaterThan)         \
   V(ArmInt8x16GreaterThanOrEqual)  \
+  V(ArmUint8x16ShiftRightByScalar) \
+  V(ArmUint8x16AddSaturate)        \
+  V(ArmUint8x16SubSaturate)        \
+  V(ArmUint8x16Min)                \
+  V(ArmUint8x16Max)                \
   V(ArmUint8x16GreaterThan)        \
   V(ArmUint8x16GreaterThanOrEqual)
 

src/compiler/arm/instruction-scheduler-arm.cc

@@ -125,6 +125,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kArmInt32x4FromFloat32x4:
     case kArmUint32x4FromFloat32x4:
     case kArmInt32x4Neg:
+    case kArmInt32x4ShiftLeftByScalar:
+    case kArmInt32x4ShiftRightByScalar:
     case kArmInt32x4Add:
     case kArmInt32x4Sub:
     case kArmInt32x4Mul:
@@ -134,6 +136,9 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kArmInt32x4NotEqual:
     case kArmInt32x4GreaterThan:
     case kArmInt32x4GreaterThanOrEqual:
+    case kArmUint32x4ShiftRightByScalar:
+    case kArmUint32x4Min:
+    case kArmUint32x4Max:
     case kArmUint32x4GreaterThan:
     case kArmUint32x4GreaterThanOrEqual:
     case kArmSimd32x4Select:
@@ -141,8 +146,12 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kArmInt16x8ExtractLane:
     case kArmInt16x8ReplaceLane:
     case kArmInt16x8Neg:
+    case kArmInt16x8ShiftLeftByScalar:
+    case kArmInt16x8ShiftRightByScalar:
     case kArmInt16x8Add:
+    case kArmInt16x8AddSaturate:
     case kArmInt16x8Sub:
+    case kArmInt16x8SubSaturate:
     case kArmInt16x8Mul:
     case kArmInt16x8Min:
     case kArmInt16x8Max:
@@ -150,14 +159,23 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kArmInt16x8NotEqual:
     case kArmInt16x8GreaterThan:
     case kArmInt16x8GreaterThanOrEqual:
+    case kArmUint16x8ShiftRightByScalar:
+    case kArmUint16x8AddSaturate:
+    case kArmUint16x8SubSaturate:
+    case kArmUint16x8Min:
+    case kArmUint16x8Max:
     case kArmUint16x8GreaterThan:
     case kArmUint16x8GreaterThanOrEqual:
     case kArmInt8x16Splat:
     case kArmInt8x16ExtractLane:
     case kArmInt8x16ReplaceLane:
     case kArmInt8x16Neg:
+    case kArmInt8x16ShiftLeftByScalar:
+    case kArmInt8x16ShiftRightByScalar:
     case kArmInt8x16Add:
+    case kArmInt8x16AddSaturate:
     case kArmInt8x16Sub:
+    case kArmInt8x16SubSaturate:
     case kArmInt8x16Mul:
     case kArmInt8x16Min:
     case kArmInt8x16Max:
@@ -165,6 +183,11 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kArmInt8x16NotEqual:
     case kArmInt8x16GreaterThan:
     case kArmInt8x16GreaterThanOrEqual:
+    case kArmUint8x16ShiftRightByScalar:
+    case kArmUint8x16AddSaturate:
+    case kArmUint8x16SubSaturate:
+    case kArmUint8x16Min:
+    case kArmUint8x16Max:
     case kArmUint8x16GreaterThan:
     case kArmUint8x16GreaterThanOrEqual:
       return kNoOpcodeFlags;

src/compiler/arm/instruction-selector-arm.cc

@@ -2190,10 +2190,14 @@ void InstructionSelector::VisitAtomicStore(Node* node) {
   V(Int32x4NotEqual)            \
   V(Int32x4GreaterThan)         \
   V(Int32x4GreaterThanOrEqual)  \
+  V(Uint32x4Min)                \
+  V(Uint32x4Max)                \
   V(Uint32x4GreaterThan)        \
   V(Uint32x4GreaterThanOrEqual) \
   V(Int16x8Add)                 \
+  V(Int16x8AddSaturate)         \
   V(Int16x8Sub)                 \
+  V(Int16x8SubSaturate)         \
   V(Int16x8Mul)                 \
   V(Int16x8Min)                 \
   V(Int16x8Max)                 \
@@ -2201,10 +2205,16 @@ void InstructionSelector::VisitAtomicStore(Node* node) {
   V(Int16x8NotEqual)            \
   V(Int16x8GreaterThan)         \
   V(Int16x8GreaterThanOrEqual)  \
+  V(Uint16x8AddSaturate)        \
+  V(Uint16x8SubSaturate)        \
+  V(Uint16x8Min)                \
+  V(Uint16x8Max)                \
   V(Uint16x8GreaterThan)        \
   V(Uint16x8GreaterThanOrEqual) \
   V(Int8x16Add)                 \
+  V(Int8x16AddSaturate)         \
   V(Int8x16Sub)                 \
+  V(Int8x16SubSaturate)         \
   V(Int8x16Mul)                 \
   V(Int8x16Min)                 \
   V(Int8x16Max)                 \
@@ -2212,9 +2222,24 @@ void InstructionSelector::VisitAtomicStore(Node* node) {
   V(Int8x16NotEqual)            \
   V(Int8x16GreaterThan)         \
   V(Int8x16GreaterThanOrEqual)  \
+  V(Uint8x16AddSaturate)        \
+  V(Uint8x16SubSaturate)        \
+  V(Uint8x16Min)                \
+  V(Uint8x16Max)                \
   V(Uint8x16GreaterThan)        \
   V(Uint8x16GreaterThanOrEqual)
 
+#define SIMD_SHIFT_OP_LIST(V)   \
+  V(Int32x4ShiftLeftByScalar)   \
+  V(Int32x4ShiftRightByScalar)  \
+  V(Uint32x4ShiftRightByScalar) \
+  V(Int16x8ShiftLeftByScalar)   \
+  V(Int16x8ShiftRightByScalar)  \
+  V(Uint16x8ShiftRightByScalar) \
+  V(Int8x16ShiftLeftByScalar)   \
+  V(Int8x16ShiftRightByScalar)  \
+  V(Uint8x16ShiftRightByScalar)
+
 #define SIMD_VISIT_SPLAT(Type)                              \
   void InstructionSelector::VisitCreate##Type(Node* node) { \
     VisitRR(this, kArm##Type##Splat, node);                 \
@@ -2250,6 +2275,13 @@ SIMD_UNOP_LIST(SIMD_VISIT_UNOP)
 SIMD_BINOP_LIST(SIMD_VISIT_BINOP)
 #undef SIMD_VISIT_BINOP
 
+#define SIMD_VISIT_SHIFT_OP(Name)                     \
+  void InstructionSelector::Visit##Name(Node* node) { \
+    VisitRRI(this, kArm##Name, node);                 \
+  }
+SIMD_SHIFT_OP_LIST(SIMD_VISIT_SHIFT_OP)
+#undef SIMD_VISIT_SHIFT_OP
+
 void InstructionSelector::VisitSimd32x4Select(Node* node) {
   ArmOperandGenerator g(this);
   Emit(kArmSimd32x4Select, g.DefineAsRegister(node),

src/compiler/code-generator-impl.h

@@ -67,6 +67,14 @@ class InstructionOperandConverter {
     return static_cast<int16_t>(InputInt32(index));
   }
 
+  uint8_t InputInt3(size_t index) {
+    return static_cast<uint8_t>(InputInt32(index) & 0x7);
+  }
+
+  uint8_t InputInt4(size_t index) {
+    return static_cast<uint8_t>(InputInt32(index) & 0xF);
+  }
+
   uint8_t InputInt5(size_t index) {
     return static_cast<uint8_t>(InputInt32(index) & 0x1F);
   }

src/compiler/instruction-selector.cc

@@ -1489,6 +1489,10 @@ void InstructionSelector::VisitNode(Node* node) {
       return MarkAsSimd128(node), VisitUint32x4FromFloat32x4(node);
     case IrOpcode::kInt32x4Neg:
       return MarkAsSimd128(node), VisitInt32x4Neg(node);
+    case IrOpcode::kInt32x4ShiftLeftByScalar:
+      return MarkAsSimd128(node), VisitInt32x4ShiftLeftByScalar(node);
+    case IrOpcode::kInt32x4ShiftRightByScalar:
+      return MarkAsSimd128(node), VisitInt32x4ShiftRightByScalar(node);
     case IrOpcode::kInt32x4Add:
       return MarkAsSimd128(node), VisitInt32x4Add(node);
     case IrOpcode::kInt32x4Sub:
@@ -1507,6 +1511,12 @@ void InstructionSelector::VisitNode(Node* node) {
       return MarkAsSimd128(node), VisitInt32x4GreaterThan(node);
     case IrOpcode::kInt32x4GreaterThanOrEqual:
       return MarkAsSimd128(node), VisitInt32x4GreaterThanOrEqual(node);
+    case IrOpcode::kUint32x4ShiftRightByScalar:
+      return MarkAsSimd128(node), VisitUint32x4ShiftRightByScalar(node);
+    case IrOpcode::kUint32x4Min:
+      return MarkAsSimd128(node), VisitUint32x4Min(node);
+    case IrOpcode::kUint32x4Max:
+      return MarkAsSimd128(node), VisitUint32x4Max(node);
     case IrOpcode::kUint32x4GreaterThan:
       return MarkAsSimd128(node), VisitUint32x4GreaterThan(node);
     case IrOpcode::kUint32x4GreaterThanOrEqual:
@@ -1521,10 +1531,18 @@ void InstructionSelector::VisitNode(Node* node) {
       return MarkAsSimd128(node), VisitInt16x8ReplaceLane(node);
     case IrOpcode::kInt16x8Neg:
       return MarkAsSimd128(node), VisitInt16x8Neg(node);
+    case IrOpcode::kInt16x8ShiftLeftByScalar:
+      return MarkAsSimd128(node), VisitInt16x8ShiftLeftByScalar(node);
+    case IrOpcode::kInt16x8ShiftRightByScalar:
+      return MarkAsSimd128(node), VisitInt16x8ShiftRightByScalar(node);
     case IrOpcode::kInt16x8Add:
       return MarkAsSimd128(node), VisitInt16x8Add(node);
+    case IrOpcode::kInt16x8AddSaturate:
+      return MarkAsSimd128(node), VisitInt16x8AddSaturate(node);
     case IrOpcode::kInt16x8Sub:
       return MarkAsSimd128(node), VisitInt16x8Sub(node);
+    case IrOpcode::kInt16x8SubSaturate:
+      return MarkAsSimd128(node), VisitInt16x8SubSaturate(node);
     case IrOpcode::kInt16x8Mul:
       return MarkAsSimd128(node), VisitInt16x8Mul(node);
     case IrOpcode::kInt16x8Min:
@@ -1539,6 +1557,16 @@ void InstructionSelector::VisitNode(Node* node) {
       return MarkAsSimd128(node), VisitInt16x8GreaterThan(node);
     case IrOpcode::kInt16x8GreaterThanOrEqual:
       return MarkAsSimd128(node), VisitInt16x8GreaterThanOrEqual(node);
+    case IrOpcode::kUint16x8ShiftRightByScalar:
+      return MarkAsSimd128(node), VisitUint16x8ShiftRightByScalar(node);
+    case IrOpcode::kUint16x8AddSaturate:
+      return MarkAsSimd128(node), VisitUint16x8AddSaturate(node);
+    case IrOpcode::kUint16x8SubSaturate:
+      return MarkAsSimd128(node), VisitUint16x8SubSaturate(node);
+    case IrOpcode::kUint16x8Min:
+      return MarkAsSimd128(node), VisitUint16x8Min(node);
+    case IrOpcode::kUint16x8Max:
+      return MarkAsSimd128(node), VisitUint16x8Max(node);
     case IrOpcode::kUint16x8GreaterThan:
       return MarkAsSimd128(node), VisitUint16x8GreaterThan(node);
     case IrOpcode::kUint16x8GreaterThanOrEqual:
@@ -1551,10 +1579,18 @@ void InstructionSelector::VisitNode(Node* node) {
       return MarkAsSimd128(node), VisitInt8x16ReplaceLane(node);
     case IrOpcode::kInt8x16Neg:
       return MarkAsSimd128(node), VisitInt8x16Neg(node);
+    case IrOpcode::kInt8x16ShiftLeftByScalar:
+      return MarkAsSimd128(node), VisitInt8x16ShiftLeftByScalar(node);
+    case IrOpcode::kInt8x16ShiftRightByScalar:
+      return MarkAsSimd128(node), VisitInt8x16ShiftRightByScalar(node);
     case IrOpcode::kInt8x16Add:
       return MarkAsSimd128(node), VisitInt8x16Add(node);
+    case IrOpcode::kInt8x16AddSaturate:
+      return MarkAsSimd128(node), VisitInt8x16AddSaturate(node);
     case IrOpcode::kInt8x16Sub:
       return MarkAsSimd128(node), VisitInt8x16Sub(node);
+    case IrOpcode::kInt8x16SubSaturate:
+      return MarkAsSimd128(node), VisitInt8x16SubSaturate(node);
     case IrOpcode::kInt8x16Mul:
       return MarkAsSimd128(node), VisitInt8x16Mul(node);
     case IrOpcode::kInt8x16Min:
@@ -1569,6 +1605,16 @@ void InstructionSelector::VisitNode(Node* node) {
       return MarkAsSimd128(node), VisitInt8x16GreaterThan(node);
     case IrOpcode::kInt8x16GreaterThanOrEqual:
       return MarkAsSimd128(node), VisitInt8x16GreaterThanOrEqual(node);
+    case IrOpcode::kUint8x16ShiftRightByScalar:
+      return MarkAsSimd128(node), VisitUint8x16ShiftRightByScalar(node);
+    case IrOpcode::kUint8x16AddSaturate:
+      return MarkAsSimd128(node), VisitUint8x16AddSaturate(node);
+    case IrOpcode::kUint8x16SubSaturate:
+      return MarkAsSimd128(node), VisitUint8x16SubSaturate(node);
+    case IrOpcode::kUint8x16Min:
+      return MarkAsSimd128(node), VisitUint8x16Min(node);
+    case IrOpcode::kUint8x16Max:
+      return MarkAsSimd128(node), VisitUint8x16Max(node);
     case IrOpcode::kUint8x16GreaterThan:
       return MarkAsSimd128(node), VisitUint8x16GreaterThan(node);
     case IrOpcode::kUint8x16GreaterThanOrEqual:
@@ -1959,6 +2005,14 @@ void InstructionSelector::VisitUint32x4FromFloat32x4(Node* node) {
 
 void InstructionSelector::VisitInt32x4Neg(Node* node) { UNIMPLEMENTED(); }
 
+void InstructionSelector::VisitInt32x4ShiftLeftByScalar(Node* node) {
+  UNIMPLEMENTED();
+}
+
+void InstructionSelector::VisitInt32x4ShiftRightByScalar(Node* node) {
+  UNIMPLEMENTED();
+}
+
 void InstructionSelector::VisitInt32x4Mul(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitInt32x4Max(Node* node) { UNIMPLEMENTED(); }
@@ -1983,6 +2037,14 @@ void InstructionSelector::VisitInt32x4GreaterThanOrEqual(Node* node) {
   UNIMPLEMENTED();
 }
 
+void InstructionSelector::VisitUint32x4ShiftRightByScalar(Node* node) {
+  UNIMPLEMENTED();
+}
+
+void InstructionSelector::VisitUint32x4Max(Node* node) { UNIMPLEMENTED(); }
+
+void InstructionSelector::VisitUint32x4Min(Node* node) { UNIMPLEMENTED(); }
+
 void InstructionSelector::VisitUint32x4GreaterThan(Node* node) {
   UNIMPLEMENTED();
 }
@@ -2005,10 +2067,26 @@ void InstructionSelector::VisitInt16x8ReplaceLane(Node* node) {
 
 void InstructionSelector::VisitInt16x8Neg(Node* node) { UNIMPLEMENTED(); }
 
+void InstructionSelector::VisitInt16x8ShiftLeftByScalar(Node* node) {
+  UNIMPLEMENTED();
+}
+
+void InstructionSelector::VisitInt16x8ShiftRightByScalar(Node* node) {
+  UNIMPLEMENTED();
+}
+
 void InstructionSelector::VisitInt16x8Add(Node* node) { UNIMPLEMENTED(); }
 
+void InstructionSelector::VisitInt16x8AddSaturate(Node* node) {
+  UNIMPLEMENTED();
+}
+
 void InstructionSelector::VisitInt16x8Sub(Node* node) { UNIMPLEMENTED(); }
 
+void InstructionSelector::VisitInt16x8SubSaturate(Node* node) {
+  UNIMPLEMENTED();
+}
+
 void InstructionSelector::VisitInt16x8Mul(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitInt16x8Max(Node* node) { UNIMPLEMENTED(); }
@@ -2033,6 +2111,22 @@ void InstructionSelector::VisitInt16x8GreaterThanOrEqual(Node* node) {
   UNIMPLEMENTED();
 }
 
+void InstructionSelector::VisitUint16x8ShiftRightByScalar(Node* node) {
+  UNIMPLEMENTED();
+}
+
+void InstructionSelector::VisitUint16x8AddSaturate(Node* node) {
+  UNIMPLEMENTED();
+}
+
+void InstructionSelector::VisitUint16x8SubSaturate(Node* node) {
+  UNIMPLEMENTED();
+}
+
+void InstructionSelector::VisitUint16x8Max(Node* node) { UNIMPLEMENTED(); }
+
+void InstructionSelector::VisitUint16x8Min(Node* node) { UNIMPLEMENTED(); }
+
 void InstructionSelector::VisitUint16x8GreaterThan(Node* node) {
   UNIMPLEMENTED();
 }
@@ -2053,10 +2147,26 @@ void InstructionSelector::VisitInt8x16ReplaceLane(Node* node) {
 
 void InstructionSelector::VisitInt8x16Neg(Node* node) { UNIMPLEMENTED(); }
 
+void InstructionSelector::VisitInt8x16ShiftLeftByScalar(Node* node) {
+  UNIMPLEMENTED();
+}
+
+void InstructionSelector::VisitInt8x16ShiftRightByScalar(Node* node) {
+  UNIMPLEMENTED();
+}
+
 void InstructionSelector::VisitInt8x16Add(Node* node) { UNIMPLEMENTED(); }
 
+void InstructionSelector::VisitInt8x16AddSaturate(Node* node) {
+  UNIMPLEMENTED();
+}
+
 void InstructionSelector::VisitInt8x16Sub(Node* node) { UNIMPLEMENTED(); }
 
+void InstructionSelector::VisitInt8x16SubSaturate(Node* node) {
+  UNIMPLEMENTED();
+}
+
 void InstructionSelector::VisitInt8x16Mul(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitInt8x16Max(Node* node) { UNIMPLEMENTED(); }
@@ -2081,6 +2191,22 @@ void InstructionSelector::VisitInt8x16GreaterThanOrEqual(Node* node) {
   UNIMPLEMENTED();
 }
 
+void InstructionSelector::VisitUint8x16ShiftRightByScalar(Node* node) {
+  UNIMPLEMENTED();
+}
+
+void InstructionSelector::VisitUint8x16AddSaturate(Node* node) {
+  UNIMPLEMENTED();
+}
+
+void InstructionSelector::VisitUint8x16SubSaturate(Node* node) {
+  UNIMPLEMENTED();
+}
+
+void InstructionSelector::VisitUint8x16Max(Node* node) { UNIMPLEMENTED(); }
+
+void InstructionSelector::VisitUint8x16Min(Node* node) { UNIMPLEMENTED(); }
+
 void InstructionSelector::VisitUint8x16GreaterThan(Node* node) {
   UNIMPLEMENTED();
 }

src/compiler/machine-operator.h

@@ -459,8 +459,8 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
   const Operator* Int32x4Mul();
   const Operator* Int32x4Min();
   const Operator* Int32x4Max();
-  const Operator* Int32x4ShiftLeftByScalar();
-  const Operator* Int32x4ShiftRightByScalar();
+  const Operator* Int32x4ShiftLeftByScalar(int32_t);
+  const Operator* Int32x4ShiftRightByScalar(int32_t);
   const Operator* Int32x4Equal();
   const Operator* Int32x4NotEqual();
   const Operator* Int32x4LessThan();
@@ -471,8 +471,7 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
 
   const Operator* Uint32x4Min();
   const Operator* Uint32x4Max();
-  const Operator* Uint32x4ShiftLeftByScalar();
-  const Operator* Uint32x4ShiftRightByScalar();
+  const Operator* Uint32x4ShiftRightByScalar(int32_t);
   const Operator* Uint32x4LessThan();
   const Operator* Uint32x4LessThanOrEqual();
   const Operator* Uint32x4GreaterThan();
@@ -480,8 +479,8 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
   const Operator* Uint32x4FromFloat32x4();
 
   const Operator* CreateBool32x4();
-  const Operator* Bool32x4ExtractLane();
-  const Operator* Bool32x4ReplaceLane();
+  const Operator* Bool32x4ExtractLane(int32_t);
+  const Operator* Bool32x4ReplaceLane(int32_t);
   const Operator* Bool32x4And();
   const Operator* Bool32x4Or();
   const Operator* Bool32x4Xor();
@@ -504,8 +503,8 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
   const Operator* Int16x8Mul();
   const Operator* Int16x8Min();
   const Operator* Int16x8Max();
-  const Operator* Int16x8ShiftLeftByScalar();
-  const Operator* Int16x8ShiftRightByScalar();
+  const Operator* Int16x8ShiftLeftByScalar(int32_t);
+  const Operator* Int16x8ShiftRightByScalar(int32_t);
   const Operator* Int16x8Equal();
   const Operator* Int16x8NotEqual();
   const Operator* Int16x8LessThan();
@@ -520,16 +519,15 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
   const Operator* Uint16x8SubSaturate();
   const Operator* Uint16x8Min();
   const Operator* Uint16x8Max();
-  const Operator* Uint16x8ShiftLeftByScalar();
-  const Operator* Uint16x8ShiftRightByScalar();
+  const Operator* Uint16x8ShiftRightByScalar(int32_t);
   const Operator* Uint16x8LessThan();
   const Operator* Uint16x8LessThanOrEqual();
   const Operator* Uint16x8GreaterThan();
   const Operator* Uint16x8GreaterThanOrEqual();
 
   const Operator* CreateBool16x8();
-  const Operator* Bool16x8ExtractLane();
-  const Operator* Bool16x8ReplaceLane();
+  const Operator* Bool16x8ExtractLane(int32_t);
+  const Operator* Bool16x8ReplaceLane(int32_t);
   const Operator* Bool16x8And();
   const Operator* Bool16x8Or();
   const Operator* Bool16x8Xor();
@@ -552,8 +550,8 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
   const Operator* Int8x16Mul();
   const Operator* Int8x16Min();
   const Operator* Int8x16Max();
-  const Operator* Int8x16ShiftLeftByScalar();
-  const Operator* Int8x16ShiftRightByScalar();
+  const Operator* Int8x16ShiftLeftByScalar(int32_t);
+  const Operator* Int8x16ShiftRightByScalar(int32_t);
   const Operator* Int8x16Equal();
   const Operator* Int8x16NotEqual();
   const Operator* Int8x16LessThan();
@@ -568,16 +566,15 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
   const Operator* Uint8x16SubSaturate();
   const Operator* Uint8x16Min();
   const Operator* Uint8x16Max();
-  const Operator* Uint8x16ShiftLeftByScalar();
-  const Operator* Uint8x16ShiftRightByScalar();
+  const Operator* Uint8x16ShiftRightByScalar(int32_t);
   const Operator* Uint8x16LessThan();
   const Operator* Uint8x16LessThanOrEqual();
   const Operator* Uint8x16GreaterThan();
   const Operator* Uint8x16GreaterThanOrEqual();
 
   const Operator* CreateBool8x16();
-  const Operator* Bool8x16ExtractLane();
-  const Operator* Bool8x16ReplaceLane();
+  const Operator* Bool8x16ExtractLane(int32_t);
+  const Operator* Bool8x16ReplaceLane(int32_t);
   const Operator* Bool8x16And();
   const Operator* Bool8x16Or();
   const Operator* Bool8x16Xor();

src/compiler/wasm-compiler.cc

@@ -3423,6 +3423,12 @@ Node* WasmGraphBuilder::SimdOp(wasm::WasmOpcode opcode,
     case wasm::kExprI32x4GeS:
       return graph()->NewNode(jsgraph()->machine()->Int32x4GreaterThanOrEqual(),
                               inputs[0], inputs[1]);
+    case wasm::kExprI32x4MinU:
+      return graph()->NewNode(jsgraph()->machine()->Uint32x4Min(), inputs[0],
+                              inputs[1]);
+    case wasm::kExprI32x4MaxU:
+      return graph()->NewNode(jsgraph()->machine()->Uint32x4Max(), inputs[0],
+                              inputs[1]);
     case wasm::kExprI32x4LtU:
       return graph()->NewNode(jsgraph()->machine()->Uint32x4GreaterThan(),
                               inputs[1], inputs[0]);
@@ -3449,9 +3455,15 @@ Node* WasmGraphBuilder::SimdOp(wasm::WasmOpcode opcode,
     case wasm::kExprI16x8Add:
       return graph()->NewNode(jsgraph()->machine()->Int16x8Add(), inputs[0],
                               inputs[1]);
+    case wasm::kExprI16x8AddSaturateS:
+      return graph()->NewNode(jsgraph()->machine()->Int16x8AddSaturate(),
+                              inputs[0], inputs[1]);
     case wasm::kExprI16x8Sub:
       return graph()->NewNode(jsgraph()->machine()->Int16x8Sub(), inputs[0],
                               inputs[1]);
+    case wasm::kExprI16x8SubSaturateS:
+      return graph()->NewNode(jsgraph()->machine()->Int16x8SubSaturate(),
+                              inputs[0], inputs[1]);
     case wasm::kExprI16x8Mul:
       return graph()->NewNode(jsgraph()->machine()->Int16x8Mul(), inputs[0],
                               inputs[1]);
@@ -3479,6 +3491,18 @@ Node* WasmGraphBuilder::SimdOp(wasm::WasmOpcode opcode,
     case wasm::kExprI16x8GeS:
       return graph()->NewNode(jsgraph()->machine()->Int16x8GreaterThanOrEqual(),
                               inputs[0], inputs[1]);
+    case wasm::kExprI16x8AddSaturateU:
+      return graph()->NewNode(jsgraph()->machine()->Uint16x8AddSaturate(),
+                              inputs[0], inputs[1]);
+    case wasm::kExprI16x8SubSaturateU:
+      return graph()->NewNode(jsgraph()->machine()->Uint16x8SubSaturate(),
+                              inputs[0], inputs[1]);
+    case wasm::kExprI16x8MinU:
+      return graph()->NewNode(jsgraph()->machine()->Uint16x8Min(), inputs[0],
+                              inputs[1]);
+    case wasm::kExprI16x8MaxU:
+      return graph()->NewNode(jsgraph()->machine()->Uint16x8Max(), inputs[0],
+                              inputs[1]);
     case wasm::kExprI16x8LtU:
       return graph()->NewNode(jsgraph()->machine()->Uint16x8GreaterThan(),
                               inputs[1], inputs[0]);
@@ -3504,9 +3528,15 @@ Node* WasmGraphBuilder::SimdOp(wasm::WasmOpcode opcode,
     case wasm::kExprI8x16Add:
       return graph()->NewNode(jsgraph()->machine()->Int8x16Add(), inputs[0],
                               inputs[1]);
+    case wasm::kExprI8x16AddSaturateS:
+      return graph()->NewNode(jsgraph()->machine()->Int8x16AddSaturate(),
+                              inputs[0], inputs[1]);
     case wasm::kExprI8x16Sub:
       return graph()->NewNode(jsgraph()->machine()->Int8x16Sub(), inputs[0],
                               inputs[1]);
+    case wasm::kExprI8x16SubSaturateS:
+      return graph()->NewNode(jsgraph()->machine()->Int8x16SubSaturate(),
+                              inputs[0], inputs[1]);
     case wasm::kExprI8x16Mul:
       return graph()->NewNode(jsgraph()->machine()->Int8x16Mul(), inputs[0],
                               inputs[1]);
@@ -3534,6 +3564,18 @@ Node* WasmGraphBuilder::SimdOp(wasm::WasmOpcode opcode,
     case wasm::kExprI8x16GeS:
       return graph()->NewNode(jsgraph()->machine()->Int8x16GreaterThanOrEqual(),
                               inputs[0], inputs[1]);
+    case wasm::kExprI8x16AddSaturateU:
+      return graph()->NewNode(jsgraph()->machine()->Uint8x16AddSaturate(),
+                              inputs[0], inputs[1]);
+    case wasm::kExprI8x16SubSaturateU:
+      return graph()->NewNode(jsgraph()->machine()->Uint8x16SubSaturate(),
+                              inputs[0], inputs[1]);
+    case wasm::kExprI8x16MinU:
+      return graph()->NewNode(jsgraph()->machine()->Uint8x16Min(), inputs[0],
+                              inputs[1]);
+    case wasm::kExprI8x16MaxU:
+      return graph()->NewNode(jsgraph()->machine()->Uint8x16Max(), inputs[0],
+                              inputs[1]);
     case wasm::kExprI8x16LtU:
       return graph()->NewNode(jsgraph()->machine()->Uint8x16GreaterThan(),
                               inputs[1], inputs[0]);
@@ -3586,6 +3628,42 @@ Node* WasmGraphBuilder::SimdLaneOp(wasm::WasmOpcode opcode, uint8_t lane,
   }
 }
 
+Node* WasmGraphBuilder::SimdShiftOp(wasm::WasmOpcode opcode, uint8_t shift,
+                                    const NodeVector& inputs) {
+  has_simd_ = true;
+  switch (opcode) {
+    case wasm::kExprI32x4Shl:
+      return graph()->NewNode(
+          jsgraph()->machine()->Int32x4ShiftLeftByScalar(shift), inputs[0]);
+    case wasm::kExprI32x4ShrS:
+      return graph()->NewNode(
+          jsgraph()->machine()->Int32x4ShiftRightByScalar(shift), inputs[0]);
+    case wasm::kExprI32x4ShrU:
+      return graph()->NewNode(
+          jsgraph()->machine()->Uint32x4ShiftRightByScalar(shift), inputs[0]);
+    case wasm::kExprI16x8Shl:
+      return graph()->NewNode(
+          jsgraph()->machine()->Int16x8ShiftLeftByScalar(shift), inputs[0]);
+    case wasm::kExprI16x8ShrS:
+      return graph()->NewNode(
+          jsgraph()->machine()->Int16x8ShiftRightByScalar(shift), inputs[0]);
+    case wasm::kExprI16x8ShrU:
+      return graph()->NewNode(
+          jsgraph()->machine()->Uint16x8ShiftRightByScalar(shift), inputs[0]);
+    case wasm::kExprI8x16Shl:
+      return graph()->NewNode(
+          jsgraph()->machine()->Int8x16ShiftLeftByScalar(shift), inputs[0]);
+    case wasm::kExprI8x16ShrS:
+      return graph()->NewNode(
+          jsgraph()->machine()->Int8x16ShiftRightByScalar(shift), inputs[0]);
+    case wasm::kExprI8x16ShrU:
+      return graph()->NewNode(
+          jsgraph()->machine()->Uint8x16ShiftRightByScalar(shift), inputs[0]);
+    default:
+      return graph()->NewNode(UnsupportedOpcode(opcode), nullptr);
+  }
+}
+
 static void RecordFunctionCompilation(CodeEventListener::LogEventsAndTags tag,
                                       Isolate* isolate, Handle<Code> code,
                                       const char* message, uint32_t index,

src/compiler/wasm-compiler.h

@@ -232,6 +232,9 @@ class WasmGraphBuilder {
   Node* SimdLaneOp(wasm::WasmOpcode opcode, uint8_t lane,
                    const NodeVector& inputs);
 
+  Node* SimdShiftOp(wasm::WasmOpcode opcode, uint8_t shift,
+                    const NodeVector& inputs);
+
   bool has_simd() const { return has_simd_; }
 
   wasm::ModuleEnv* module_env() const { return module_; }

src/wasm/function-body-decoder.cc

@@ -149,16 +149,28 @@ struct Control {
   (build() ? CheckForException(builder_->func(__VA_ARGS__)) : nullptr)
 #define BUILD0(func) (build() ? CheckForException(builder_->func()) : nullptr)
 
-struct LaneOperand {
+// Operand for SIMD lane operations.
+struct SimdLaneOperand {
   uint8_t lane;
   unsigned length;
 
-  inline LaneOperand(Decoder* decoder, const byte* pc) {
+  inline SimdLaneOperand(Decoder* decoder, const byte* pc) {
     lane = decoder->checked_read_u8(pc, 2, "lane");
     length = 1;
   }
 };
 
+// Operand for SIMD shift operations.
+struct SimdShiftOperand {
+  uint8_t shift;
+  unsigned length;
+
+  inline SimdShiftOperand(Decoder* decoder, const byte* pc) {
+    shift = decoder->checked_read_u8(pc, 2, "shift");
+    length = 1;
+  }
+};
+
 // Generic Wasm bytecode decoder with utilities for decoding operands,
 // lengths, etc.
 class WasmDecoder : public Decoder {
@@ -350,7 +362,7 @@ class WasmDecoder : public Decoder {
   }
 
   inline bool Validate(const byte* pc, WasmOpcode opcode,
-                       LaneOperand& operand) {
+                       SimdLaneOperand& operand) {
     uint8_t num_lanes = 0;
     switch (opcode) {
       case kExprF32x4ExtractLane:
@@ -372,7 +384,38 @@ class WasmDecoder : public Decoder {
         break;
     }
     if (operand.lane < 0 || operand.lane >= num_lanes) {
-      error(pc_, pc_ + 2, "invalid lane value");
+      error(pc_, pc_ + 2, "invalid lane index");
+      return false;
+    } else {
+      return true;
+    }
+  }
+
+  inline bool Validate(const byte* pc, WasmOpcode opcode,
+                       SimdShiftOperand& operand) {
+    uint8_t max_shift = 0;
+    switch (opcode) {
+      case kExprI32x4Shl:
+      case kExprI32x4ShrS:
+      case kExprI32x4ShrU:
+        max_shift = 32;
+        break;
+      case kExprI16x8Shl:
+      case kExprI16x8ShrS:
+      case kExprI16x8ShrU:
+        max_shift = 16;
+        break;
+      case kExprI8x16Shl:
+      case kExprI8x16ShrS:
+      case kExprI8x16ShrU:
+        max_shift = 8;
+        break;
+      default:
+        UNREACHABLE();
+        break;
+    }
+    if (operand.shift < 0 || operand.shift >= max_shift) {
+      error(pc_, pc_ + 2, "invalid shift amount");
       return false;
     } else {
       return true;
@@ -1369,8 +1412,8 @@ class WasmFullDecoder : public WasmDecoder {
     return 1 + operand.length;
   }
 
-  unsigned ExtractLane(WasmOpcode opcode, ValueType type) {
-    LaneOperand operand(this, pc_);
+  unsigned SimdExtractLane(WasmOpcode opcode, ValueType type) {
+    SimdLaneOperand operand(this, pc_);
     if (Validate(pc_, opcode, operand)) {
       compiler::NodeVector inputs(1, zone_);
       inputs[0] = Pop(0, ValueType::kSimd128).node;
@@ -1380,8 +1423,8 @@ class WasmFullDecoder : public WasmDecoder {
     return operand.length;
   }
 
-  unsigned ReplaceLane(WasmOpcode opcode, ValueType type) {
-    LaneOperand operand(this, pc_);
+  unsigned SimdReplaceLane(WasmOpcode opcode, ValueType type) {
+    SimdLaneOperand operand(this, pc_);
     if (Validate(pc_, opcode, operand)) {
       compiler::NodeVector inputs(2, zone_);
       inputs[1] = Pop(1, type).node;
@@ -1392,27 +1435,50 @@ class WasmFullDecoder : public WasmDecoder {
     return operand.length;
   }
 
+  unsigned SimdShiftOp(WasmOpcode opcode) {
+    SimdShiftOperand operand(this, pc_);
+    if (Validate(pc_, opcode, operand)) {
+      compiler::NodeVector inputs(1, zone_);
+      inputs[0] = Pop(0, ValueType::kSimd128).node;
+      TFNode* node = BUILD(SimdShiftOp, opcode, operand.shift, inputs);
+      Push(ValueType::kSimd128, node);
+    }
+    return operand.length;
+  }
+
   unsigned DecodeSimdOpcode(WasmOpcode opcode) {
     unsigned len = 0;
     switch (opcode) {
       case kExprF32x4ExtractLane: {
-        len = ExtractLane(opcode, ValueType::kFloat32);
+        len = SimdExtractLane(opcode, ValueType::kFloat32);
         break;
       }
       case kExprI32x4ExtractLane:
       case kExprI16x8ExtractLane:
       case kExprI8x16ExtractLane: {
-        len = ExtractLane(opcode, ValueType::kWord32);
+        len = SimdExtractLane(opcode, ValueType::kWord32);
         break;
       }
       case kExprF32x4ReplaceLane: {
-        len = ReplaceLane(opcode, ValueType::kFloat32);
+        len = SimdReplaceLane(opcode, ValueType::kFloat32);
         break;
       }
       case kExprI32x4ReplaceLane:
       case kExprI16x8ReplaceLane:
       case kExprI8x16ReplaceLane: {
-        len = ReplaceLane(opcode, ValueType::kWord32);
+        len = SimdReplaceLane(opcode, ValueType::kWord32);
+        break;
+      }
+      case kExprI32x4Shl:
+      case kExprI32x4ShrS:
+      case kExprI32x4ShrU:
+      case kExprI16x8Shl:
+      case kExprI16x8ShrS:
+      case kExprI16x8ShrU:
+      case kExprI8x16Shl:
+      case kExprI8x16ShrS:
+      case kExprI8x16ShrU: {
+        len = SimdShiftOp(opcode);
         break;
       }
       default: {

src/wasm/wasm-macro-gen.h

@@ -460,9 +460,6 @@ class LocalDeclEncoder {
       static_cast<byte>(index)
 #define WASM_UNOP(opcode, x) x, static_cast<byte>(opcode)
 #define WASM_BINOP(opcode, x, y) x, y, static_cast<byte>(opcode)
-#define WASM_SIMD_UNOP(opcode, x) x, kSimdPrefix, static_cast<byte>(opcode)
-#define WASM_SIMD_BINOP(opcode, x, y) \
-  x, y, kSimdPrefix, static_cast<byte>(opcode)
 
 //------------------------------------------------------------------------------
 // Int32 operations

src/wasm/wasm-opcodes.h

@@ -303,8 +303,6 @@ const WasmCodePosition kNoCodePosition = -1;
   V(I32x4Mul, 0xe521, s_ss)              \
   V(I32x4MinS, 0xe522, s_ss)             \
   V(I32x4MaxS, 0xe523, s_ss)             \
-  V(I32x4Shl, 0xe524, s_si)              \
-  V(I32x4ShrS, 0xe525, s_si)             \
   V(I32x4Eq, 0xe526, s_ss)               \
   V(I32x4Ne, 0xe527, s_ss)               \
   V(I32x4LtS, 0xe528, s_ss)              \
@@ -317,7 +315,6 @@ const WasmCodePosition kNoCodePosition = -1;
   V(I32x4SConvertF32x4, 0xe52f, s_s)     \
   V(I32x4MinU, 0xe530, s_ss)             \
   V(I32x4MaxU, 0xe531, s_ss)             \
-  V(I32x4ShrU, 0xe532, s_ss)             \
   V(I32x4LtU, 0xe533, s_ss)              \
   V(I32x4LeU, 0xe534, s_ss)              \
   V(I32x4GtU, 0xe535, s_ss)              \
@@ -332,8 +329,6 @@ const WasmCodePosition kNoCodePosition = -1;
   V(I16x8Mul, 0xe540, s_ss)              \
   V(I16x8MinS, 0xe541, s_ss)             \
   V(I16x8MaxS, 0xe542, s_ss)             \
-  V(I16x8Shl, 0xe543, s_si)              \
-  V(I16x8ShrS, 0xe544, s_si)             \
   V(I16x8Eq, 0xe545, s_ss)               \
   V(I16x8Ne, 0xe546, s_ss)               \
   V(I16x8LtS, 0xe547, s_ss)              \
@@ -347,7 +342,6 @@ const WasmCodePosition kNoCodePosition = -1;
   V(I16x8SubSaturateU, 0xe54f, s_ss)     \
   V(I16x8MinU, 0xe550, s_ss)             \
   V(I16x8MaxU, 0xe551, s_ss)             \
-  V(I16x8ShrU, 0xe552, s_si)             \
   V(I16x8LtU, 0xe553, s_ss)              \
   V(I16x8LeU, 0xe554, s_ss)              \
   V(I16x8GtU, 0xe555, s_ss)              \
@@ -361,8 +355,6 @@ const WasmCodePosition kNoCodePosition = -1;
   V(I8x16Mul, 0xe55f, s_ss)              \
   V(I8x16MinS, 0xe560, s_ss)             \
   V(I8x16MaxS, 0xe561, s_ss)             \
-  V(I8x16Shl, 0xe562, s_si)              \
-  V(I8x16ShrS, 0xe563, s_si)             \
   V(I8x16Eq, 0xe564, s_ss)               \
   V(I8x16Ne, 0xe565, s_ss)               \
   V(I8x16LtS, 0xe566, s_ss)              \
@@ -376,7 +368,6 @@ const WasmCodePosition kNoCodePosition = -1;
   V(I8x16SubSaturateU, 0xe56e, s_ss)     \
   V(I8x16MinU, 0xe56f, s_ss)             \
   V(I8x16MaxU, 0xe570, s_ss)             \
-  V(I8x16ShrU, 0xe571, s_ss)             \
   V(I8x16LtU, 0xe572, s_ss)              \
   V(I8x16LeU, 0xe573, s_ss)              \
   V(I8x16GtU, 0xe574, s_ss)              \
@@ -394,10 +385,19 @@ const WasmCodePosition kNoCodePosition = -1;
   V(F32x4ReplaceLane, 0xe502, _)         \
   V(I32x4ExtractLane, 0xe51c, _)         \
   V(I32x4ReplaceLane, 0xe51d, _)         \
+  V(I32x4Shl, 0xe524, _)                 \
+  V(I32x4ShrS, 0xe525, _)                \
+  V(I32x4ShrU, 0xe532, _)                \
   V(I16x8ExtractLane, 0xe539, _)         \
   V(I16x8ReplaceLane, 0xe53a, _)         \
+  V(I16x8Shl, 0xe543, _)                 \
+  V(I16x8ShrS, 0xe544, _)                \
+  V(I16x8ShrU, 0xe552, _)                \
   V(I8x16ExtractLane, 0xe558, _)         \
-  V(I8x16ReplaceLane, 0xe559, _)
+  V(I8x16ReplaceLane, 0xe559, _)         \
+  V(I8x16Shl, 0xe562, _)                 \
+  V(I8x16ShrS, 0xe563, _)                \
+  V(I8x16ShrU, 0xe571, _)
 
 #define FOREACH_ATOMIC_OPCODE(V)               \
   V(I32AtomicAdd8S, 0xe601, i_ii)              \