Commit 031193b4 authored by Ng Zhi An's avatar Ng Zhi An Committed by Commit Bot

[wasm-simd] Convert some codegen to use macros

The macros will use AVX variants when available.

Bug: v8:9561
Change-Id: I06872a08184983adc8018ffdf03916feac02016f
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1857422Reviewed-by: 's avatarDeepti Gandluri <gdeepti@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#64280}
parent 74996b4e
......@@ -156,6 +156,7 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
AVX_OP(Ucomisd, ucomisd)
AVX_OP(Pshufb, pshufb)
AVX_OP(Paddusb, paddusb)
AVX_OP(Sqrtpd, sqrtpd)
#undef AVX_OP
......
......@@ -2293,7 +2293,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
}
case kX64F64x2Sqrt: {
__ sqrtpd(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ Sqrtpd(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kX64F64x2Add: {
......@@ -2353,22 +2353,22 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
}
case kX64F64x2Eq: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ cmpeqpd(i.OutputSimd128Register(), i.InputSimd128Register(1));
__ Cmpeqpd(i.OutputSimd128Register(), i.InputSimd128Register(1));
break;
}
case kX64F64x2Ne: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ cmpneqpd(i.OutputSimd128Register(), i.InputSimd128Register(1));
__ Cmpneqpd(i.OutputSimd128Register(), i.InputSimd128Register(1));
break;
}
case kX64F64x2Lt: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ cmpltpd(i.OutputSimd128Register(), i.InputSimd128Register(1));
__ Cmpltpd(i.OutputSimd128Register(), i.InputSimd128Register(1));
break;
}
case kX64F64x2Le: {
DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
__ cmplepd(i.OutputSimd128Register(), i.InputSimd128Register(1));
__ Cmplepd(i.OutputSimd128Register(), i.InputSimd128Register(1));
break;
}
case kX64F64x2Qfma: {
......
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