[wasm-simd][x64] Consolidate some instructions into macro list

These operations can be moved into an existing macro list, since they
are simple operations that generate only 1 instruction. The benefit is
that they have support for AVX 3-operand instruction, and does not have
to force dst to be equals to src.

Bug: v8:9561
Change-Id: I9ec1d2496d14cb9f0fb3b4854ca39887eb5bf49b
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2505240Reviewed-by: Clemens Backes <clemensb@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#70893}

src/compiler/backend/x64/code-generator-x64.cc

@@ -2810,8 +2810,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       break;
     }
     case kX64I64x2Eq: {
-      DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
-      __ Pcmpeqq(i.OutputSimd128Register(), i.InputSimd128Register(1));
+      ASSEMBLE_SIMD_BINOP(pcmpeqq);
       break;
     }
     case kX64I64x2ShrU: {
@@ -3154,8 +3153,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       break;
     }
     case kX64I16x8UConvertI32x4: {
-      DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
-      __ Packusdw(i.OutputSimd128Register(), i.InputSimd128Register(1));
+      ASSEMBLE_SIMD_BINOP(packusdw);
       break;
     }
     case kX64I16x8AddSatU: {
@@ -3427,8 +3425,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       break;
     }
     case kX64I8x16UConvertI16x8: {
-      DCHECK_EQ(i.OutputSimd128Register(), i.InputSimd128Register(0));
-      __ Packuswb(i.OutputSimd128Register(), i.InputSimd128Register(1));
+      ASSEMBLE_SIMD_BINOP(packuswb);
       break;
     }
     case kX64I8x16ShrU: {

src/compiler/backend/x64/instruction-selector-x64.cc

@@ -2819,6 +2819,7 @@ VISIT_ATOMIC_BINOP(Xor)
   V(F32x4Le)                       \
   V(I64x2Add)                      \
   V(I64x2Sub)                      \
+  V(I64x2Eq)                       \
   V(I32x4Add)                      \
   V(I32x4AddHoriz)                 \
   V(I32x4Sub)                      \
@@ -2831,6 +2832,7 @@ VISIT_ATOMIC_BINOP(Xor)
   V(I32x4MaxU)                     \
   V(I32x4DotI16x8S)                \
   V(I16x8SConvertI32x4)            \
+  V(I16x8UConvertI32x4)            \
   V(I16x8Add)                      \
   V(I16x8AddSatS)                  \
   V(I16x8AddHoriz)                 \
@@ -2847,6 +2849,7 @@ VISIT_ATOMIC_BINOP(Xor)
   V(I16x8MaxU)                     \
   V(I16x8RoundingAverageU)         \
   V(I8x16SConvertI16x8)            \
+  V(I8x16UConvertI16x8)            \
   V(I8x16Add)                      \
   V(I8x16AddSatS)                  \
   V(I8x16Sub)                      \
@@ -2870,7 +2873,6 @@ VISIT_ATOMIC_BINOP(Xor)
   V(F32x4AddHoriz)         \
   V(F32x4Min)              \
   V(F32x4Max)              \
-  V(I64x2Eq)               \
   V(I32x4GeS)              \
   V(I32x4GeU)              \
   V(I16x8GeS)              \
@@ -3258,12 +3260,6 @@ void InstructionSelector::VisitI32x4UConvertF32x4(Node* node) {
        g.UseRegister(node->InputAt(0)), arraysize(temps), temps);
 }
 
-void InstructionSelector::VisitI16x8UConvertI32x4(Node* node) {
-  X64OperandGenerator g(this);
-  Emit(kX64I16x8UConvertI32x4, g.DefineSameAsFirst(node),
-       g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
-}
-
 void InstructionSelector::VisitI16x8BitMask(Node* node) {
   X64OperandGenerator g(this);
   InstructionOperand temps[] = {g.TempSimd128Register()};
@@ -3271,12 +3267,6 @@ void InstructionSelector::VisitI16x8BitMask(Node* node) {
        g.UseUniqueRegister(node->InputAt(0)), arraysize(temps), temps);
 }
 
-void InstructionSelector::VisitI8x16UConvertI16x8(Node* node) {
-  X64OperandGenerator g(this);
-  Emit(kX64I8x16UConvertI16x8, g.DefineSameAsFirst(node),
-       g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
-}
-
 void InstructionSelector::VisitI8x16Mul(Node* node) {
   X64OperandGenerator g(this);
   InstructionOperand temps[] = {g.TempSimd128Register()};