Simd128Registers::names_ is also removed as the stringification
will be done by DEFINE_REGISTER_NAMES.

PPC FP and Vector Register (VR and VSR) Layou:

VR0 is VSR32 and goes all the way to VSR63 which is used by V8 Vector
operations.

VSR[0]0 - FPR[0]                     VSR[0]128
  |
  |
  |
VSR[31] - FPR[31]
VSR[32] - VR[0]                      VR[0]128
  |
  |
  |
  V
VSR[63] - VR[31]

Change-Id: Ied2a530b08d1eb40af59ce44f848d638f2a6dc9f
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2587356Reviewed-by: Junliang Yan <junyan@redhat.com>
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/master@{#71735}