When running under simulator, all arm64 JIT instructions are interpreted by
simulator via normal memory read, then no need to do icache/dcache flush.

Also when running under simulator, cache_type_register_ is set to 0 explicitly
in above CacheLineSizes class, which results in 0 value in both dstart and
istart, then causes flush on this incorrect range.

Bug: chromium:893460
Change-Id: Ief6cb09a0e89f7ede0761ad676ea6a882e9f4600
Reviewed-on: https://chromium-review.googlesource.com/c/1492514
Commit-Queue: Michael Lippautz <mlippautz@chromium.org>
Reviewed-by: Michael Lippautz <mlippautz@chromium.org>
Cr-Commit-Position: refs/heads/master@{#59987}