• ivica.bogosavljevic's avatar
    MIPS64: Port `ARM64: [turbofan] Avoid zero-extension after a 32-bit load` · 4125ba8b
    ivica.bogosavljevic authored
    Port f07d2cdd
    
    Original commit message:
    A load instruction will implicitely clear the top 32 bits when writing to a W
    register. This patch avoids generating a `mov` instruction to zero-extend the
    result in this case.
    
    For example, this occurs in the generated code for dispatching to the next
    bytecode in the interpreter:
    
      kind = BYTECODE_HANDLER
      name = LdaZero
      compiler = turbofan
      Instructions (size = 36)
      0x32e64c60     0  add x19, x19, #0x1 (1)
      0x32e64c64     4  ldrb w0, [x20, x19]
      0x32e64c68     8  mov w0, w0
                        ^^^^^^^^^^
      0x32e64c6c    12  lsl x0, x0, #3
      0x32e64c70    16  ldr x1, [x21, x0]
      0x32e64c74    20  movz x0, #0x0
      0x32e64c78    24  br x1
    
    Review-Url: https://codereview.chromium.org/2469253002
    Cr-Commit-Position: refs/heads/master@{#40758}
    4125ba8b
instruction-selector-mips64.cc 88.4 KB