cpu-features.h 3.11 KB
Newer Older
1 2 3 4
// Copyright 2018 the V8 project authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.

5 6
#ifndef V8_CODEGEN_CPU_FEATURES_H_
#define V8_CODEGEN_CPU_FEATURES_H_
7

8
#include "src/common/globals.h"
9 10 11 12 13 14 15

namespace v8 {

namespace internal {

// CPU feature flags.
enum CpuFeature {
16
#if V8_TARGET_ARCH_IA32 || V8_TARGET_ARCH_X64
17
  SSE4_2,
18 19 20 21 22
  SSE4_1,
  SSSE3,
  SSE3,
  SAHF,
  AVX,
Zhi An Ng's avatar
Zhi An Ng committed
23
  AVX2,
24 25 26 27 28 29
  FMA3,
  BMI1,
  BMI2,
  LZCNT,
  POPCNT,
  ATOM,
30

31
#elif V8_TARGET_ARCH_ARM
32 33 34 35
  // - Standard configurations. The baseline is ARMv6+VFPv2.
  ARMv7,        // ARMv7-A + VFPv3-D32 + NEON
  ARMv7_SUDIV,  // ARMv7-A + VFPv4-D32 + NEON + SUDIV
  ARMv8,        // ARMv8-A (+ all of the above)
36 37 38 39 40 41 42

  // ARM feature aliases (based on the standard configurations above).
  VFPv3 = ARMv7,
  NEON = ARMv7,
  VFP32DREGS = ARMv7,
  SUDIV = ARMv7_SUDIV,

43 44 45
#elif V8_TARGET_ARCH_ARM64
  JSCVT,

46
#elif V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64
47 48 49 50 51 52
  FPU,
  FP64FPU,
  MIPSr1,
  MIPSr2,
  MIPSr6,
  MIPS_SIMD,  // MSA instructions
53

54
#elif V8_TARGET_ARCH_PPC || V8_TARGET_ARCH_PPC64
55
  FPU,
56 57 58 59 60
  FPR_GPR_MOV,
  LWSYNC,
  ISELECT,
  VSX,
  MODULO,
61 62 63

#elif V8_TARGET_ARCH_S390X
  FPU,
64 65 66 67
  DISTINCT_OPS,
  GENERAL_INSTR_EXT,
  FLOATING_POINT_EXT,
  VECTOR_FACILITY,
68
  VECTOR_ENHANCE_FACILITY_1,
69
  VECTOR_ENHANCE_FACILITY_2,
70
  MISC_INSTR_EXT2,
71
#endif
72

73
  NUMBER_OF_CPU_FEATURES
74 75 76 77 78 79 80 81 82 83 84
};

// CpuFeatures keeps track of which features are supported by the target CPU.
// Supported features must be enabled by a CpuFeatureScope before use.
// Example:
//   if (assembler->IsSupported(SSE3)) {
//     CpuFeatureScope fscope(assembler, SSE3);
//     // Generate code containing SSE3 instructions.
//   } else {
//     // Generate alternative code.
//   }
85
class V8_EXPORT_PRIVATE CpuFeatures : public AllStatic {
86
 public:
87 88 89
  CpuFeatures(const CpuFeatures&) = delete;
  CpuFeatures& operator=(const CpuFeatures&) = delete;

90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123
  static void Probe(bool cross_compile) {
    STATIC_ASSERT(NUMBER_OF_CPU_FEATURES <= kBitsPerInt);
    if (initialized_) return;
    initialized_ = true;
    ProbeImpl(cross_compile);
  }

  static unsigned SupportedFeatures() {
    Probe(false);
    return supported_;
  }

  static bool IsSupported(CpuFeature f) {
    return (supported_ & (1u << f)) != 0;
  }

  static inline bool SupportsOptimizer();

  static inline bool SupportsWasmSimd128();

  static inline unsigned icache_line_size() {
    DCHECK_NE(icache_line_size_, 0);
    return icache_line_size_;
  }

  static inline unsigned dcache_line_size() {
    DCHECK_NE(dcache_line_size_, 0);
    return dcache_line_size_;
  }

  static void PrintTarget();
  static void PrintFeatures();

 private:
124
  friend void V8_EXPORT_PRIVATE FlushInstructionCache(void*, size_t);
125 126 127 128 129 130 131 132 133 134 135 136 137 138 139
  friend class ExternalReference;
  // Flush instruction cache.
  static void FlushICache(void* start, size_t size);

  // Platform-dependent implementation.
  static void ProbeImpl(bool cross_compile);

  static unsigned supported_;
  static unsigned icache_line_size_;
  static unsigned dcache_line_size_;
  static bool initialized_;
};

}  // namespace internal
}  // namespace v8
140
#endif  // V8_CODEGEN_CPU_FEATURES_H_