disasm-ia32.cc 38.5 KB
Newer Older
1
// Copyright 2007-2008 the V8 project authors. All rights reserved.
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
//     * Redistributions of source code must retain the above copyright
//       notice, this list of conditions and the following disclaimer.
//     * Redistributions in binary form must reproduce the above
//       copyright notice, this list of conditions and the following
//       disclaimer in the documentation and/or other materials provided
//       with the distribution.
//     * Neither the name of Google Inc. nor the names of its
//       contributors may be used to endorse or promote products derived
//       from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

#include <assert.h>
#include <stdio.h>
#include <stdarg.h>
31 32

#include "v8.h"
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
#include "disasm.h"

namespace disasm {

enum OperandOrder {
  UNSET_OP_ORDER = 0,
  REG_OPER_OP_ORDER,
  OPER_REG_OP_ORDER
};


//------------------------------------------------------------------
// Tables
//------------------------------------------------------------------
struct ByteMnemonic {
  int b;  // -1 terminates, otherwise must be in range (0..255)
  const char* mnem;
  OperandOrder op_order_;
};


static ByteMnemonic two_operands_instr[] = {
  {0x03, "add", REG_OPER_OP_ORDER},
  {0x21, "and", OPER_REG_OP_ORDER},
  {0x23, "and", REG_OPER_OP_ORDER},
  {0x3B, "cmp", REG_OPER_OP_ORDER},
  {0x8D, "lea", REG_OPER_OP_ORDER},
  {0x09, "or", OPER_REG_OP_ORDER},
  {0x0B, "or", REG_OPER_OP_ORDER},
  {0x1B, "sbb", REG_OPER_OP_ORDER},
  {0x29, "sub", OPER_REG_OP_ORDER},
64
  {0x2A, "subb", REG_OPER_OP_ORDER},
65
  {0x2B, "sub", REG_OPER_OP_ORDER},
66
  {0x84, "test_b", REG_OPER_OP_ORDER},
67 68 69
  {0x85, "test", REG_OPER_OP_ORDER},
  {0x31, "xor", OPER_REG_OP_ORDER},
  {0x33, "xor", REG_OPER_OP_ORDER},
70
  {0x87, "xchg", REG_OPER_OP_ORDER},
71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
  {0x8A, "mov_b", REG_OPER_OP_ORDER},
  {0x8B, "mov", REG_OPER_OP_ORDER},
  {-1, "", UNSET_OP_ORDER}
};


static ByteMnemonic zero_operands_instr[] = {
  {0xC3, "ret", UNSET_OP_ORDER},
  {0xC9, "leave", UNSET_OP_ORDER},
  {0x90, "nop", UNSET_OP_ORDER},
  {0xF4, "hlt", UNSET_OP_ORDER},
  {0xCC, "int3", UNSET_OP_ORDER},
  {0x60, "pushad", UNSET_OP_ORDER},
  {0x61, "popad", UNSET_OP_ORDER},
  {0x9C, "pushfd", UNSET_OP_ORDER},
  {0x9D, "popfd", UNSET_OP_ORDER},
  {0x9E, "sahf", UNSET_OP_ORDER},
  {0x99, "cdq", UNSET_OP_ORDER},
  {0x9B, "fwait", UNSET_OP_ORDER},
  {-1, "", UNSET_OP_ORDER}
};


static ByteMnemonic call_jump_instr[] = {
  {0xE8, "call", UNSET_OP_ORDER},
  {0xE9, "jmp", UNSET_OP_ORDER},
  {-1, "", UNSET_OP_ORDER}
};


static ByteMnemonic short_immediate_instr[] = {
  {0x05, "add", UNSET_OP_ORDER},
  {0x0D, "or", UNSET_OP_ORDER},
  {0x15, "adc", UNSET_OP_ORDER},
  {0x25, "and", UNSET_OP_ORDER},
  {0x2D, "sub", UNSET_OP_ORDER},
  {0x35, "xor", UNSET_OP_ORDER},
  {0x3D, "cmp", UNSET_OP_ORDER},
  {-1, "", UNSET_OP_ORDER}
};


static const char* jump_conditional_mnem[] = {
  /*0*/ "jo", "jno", "jc", "jnc",
  /*4*/ "jz", "jnz", "jna", "ja",
  /*8*/ "js", "jns", "jpe", "jpo",
  /*12*/ "jl", "jnl", "jng", "jg"
};


121 122 123 124 125 126 127 128
static const char* set_conditional_mnem[] = {
  /*0*/ "seto", "setno", "setc", "setnc",
  /*4*/ "setz", "setnz", "setna", "seta",
  /*8*/ "sets", "setns", "setpe", "setpo",
  /*12*/ "setl", "setnl", "setng", "setg"
};


129 130 131 132 133 134 135 136
static const char* conditional_move_mnem[] = {
  /*0*/ "cmovo", "cmovno", "cmovc", "cmovnc",
  /*4*/ "cmovz", "cmovnz", "cmovna", "cmova",
  /*8*/ "cmovs", "cmovns", "cmovpe", "cmovpo",
  /*12*/ "cmovl", "cmovnl", "cmovng", "cmovg"
};


137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198
enum InstructionType {
  NO_INSTR,
  ZERO_OPERANDS_INSTR,
  TWO_OPERANDS_INSTR,
  JUMP_CONDITIONAL_SHORT_INSTR,
  REGISTER_INSTR,
  MOVE_REG_INSTR,
  CALL_JUMP_INSTR,
  SHORT_IMMEDIATE_INSTR
};


struct InstructionDesc {
  const char* mnem;
  InstructionType type;
  OperandOrder op_order_;
};


class InstructionTable {
 public:
  InstructionTable();
  const InstructionDesc& Get(byte x) const { return instructions_[x]; }

 private:
  InstructionDesc instructions_[256];
  void Clear();
  void Init();
  void CopyTable(ByteMnemonic bm[], InstructionType type);
  void SetTableRange(InstructionType type,
                     byte start,
                     byte end,
                     const char* mnem);
  void AddJumpConditionalShort();
};


InstructionTable::InstructionTable() {
  Clear();
  Init();
}


void InstructionTable::Clear() {
  for (int i = 0; i < 256; i++) {
    instructions_[i].mnem = "";
    instructions_[i].type = NO_INSTR;
    instructions_[i].op_order_ = UNSET_OP_ORDER;
  }
}


void InstructionTable::Init() {
  CopyTable(two_operands_instr, TWO_OPERANDS_INSTR);
  CopyTable(zero_operands_instr, ZERO_OPERANDS_INSTR);
  CopyTable(call_jump_instr, CALL_JUMP_INSTR);
  CopyTable(short_immediate_instr, SHORT_IMMEDIATE_INSTR);
  AddJumpConditionalShort();
  SetTableRange(REGISTER_INSTR, 0x40, 0x47, "inc");
  SetTableRange(REGISTER_INSTR, 0x48, 0x4F, "dec");
  SetTableRange(REGISTER_INSTR, 0x50, 0x57, "push");
  SetTableRange(REGISTER_INSTR, 0x58, 0x5F, "pop");
199
  SetTableRange(REGISTER_INSTR, 0x91, 0x97, "xchg eax,");  // 0x90 is nop.
200 201 202 203 204 205 206 207 208
  SetTableRange(MOVE_REG_INSTR, 0xB8, 0xBF, "mov");
}


void InstructionTable::CopyTable(ByteMnemonic bm[], InstructionType type) {
  for (int i = 0; bm[i].b >= 0; i++) {
    InstructionDesc* id = &instructions_[bm[i].b];
    id->mnem = bm[i].mnem;
    id->op_order_ = bm[i].op_order_;
209
    ASSERT_EQ(NO_INSTR, id->type);  // Information not already entered.
210 211 212 213 214 215 216 217 218 219 220
    id->type = type;
  }
}


void InstructionTable::SetTableRange(InstructionType type,
                                     byte start,
                                     byte end,
                                     const char* mnem) {
  for (byte b = start; b <= end; b++) {
    InstructionDesc* id = &instructions_[b];
221
    ASSERT_EQ(NO_INSTR, id->type);  // Information not already entered.
222 223 224 225 226 227 228 229 230
    id->mnem = mnem;
    id->type = type;
  }
}


void InstructionTable::AddJumpConditionalShort() {
  for (byte b = 0x70; b <= 0x7F; b++) {
    InstructionDesc* id = &instructions_[b];
231
    ASSERT_EQ(NO_INSTR, id->type);  // Information not already entered.
232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255
    id->mnem = jump_conditional_mnem[b & 0x0F];
    id->type = JUMP_CONDITIONAL_SHORT_INSTR;
  }
}


static InstructionTable instruction_table;


// The IA32 disassembler implementation.
class DisassemblerIA32 {
 public:
  DisassemblerIA32(const NameConverter& converter,
                   bool abort_on_unimplemented = true)
      : converter_(converter),
        tmp_buffer_pos_(0),
        abort_on_unimplemented_(abort_on_unimplemented) {
    tmp_buffer_[0] = '\0';
  }

  virtual ~DisassemblerIA32() {}

  // Writes one disassembled instruction into 'buffer' (0-terminated).
  // Returns the length of the disassembled machine instruction in bytes.
256
  int InstructionDecode(v8::internal::Vector<char> buffer, byte* instruction);
257 258 259

 private:
  const NameConverter& converter_;
260
  v8::internal::EmbeddedVector<char, 128> tmp_buffer_;
261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276
  unsigned int tmp_buffer_pos_;
  bool abort_on_unimplemented_;


  enum {
    eax = 0,
    ecx = 1,
    edx = 2,
    ebx = 3,
    esp = 4,
    ebp = 5,
    esi = 6,
    edi = 7
  };


277 278 279 280 281 282 283 284 285 286 287
  enum ShiftOpcodeExtension {
    kROL = 0,
    kROR = 1,
    kRCL = 2,
    kRCR = 3,
    kSHL = 4,
    KSHR = 5,
    kSAR = 7
  };


288 289 290 291 292
  const char* NameOfCPURegister(int reg) const {
    return converter_.NameOfCPURegister(reg);
  }


293 294 295 296 297
  const char* NameOfByteCPURegister(int reg) const {
    return converter_.NameOfByteCPURegister(reg);
  }


298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321
  const char* NameOfXMMRegister(int reg) const {
    return converter_.NameOfXMMRegister(reg);
  }


  const char* NameOfAddress(byte* addr) const {
    return converter_.NameOfAddress(addr);
  }


  // Disassembler helper functions.
  static void get_modrm(byte data, int* mod, int* regop, int* rm) {
    *mod = (data >> 6) & 3;
    *regop = (data & 0x38) >> 3;
    *rm = data & 7;
  }


  static void get_sib(byte data, int* scale, int* index, int* base) {
    *scale = (data >> 6) & 3;
    *index = (data >> 3) & 7;
    *base = data & 7;
  }

322
  typedef const char* (DisassemblerIA32::*RegisterNameMapping)(int reg) const;
323

324
  int PrintRightOperandHelper(byte* modrmp, RegisterNameMapping register_name);
325
  int PrintRightOperand(byte* modrmp);
326
  int PrintRightByteOperand(byte* modrmp);
327 328 329 330 331 332 333
  int PrintOperands(const char* mnem, OperandOrder op_order, byte* data);
  int PrintImmediateOp(byte* data);
  int F7Instruction(byte* data);
  int D1D3C1Instruction(byte* data);
  int JumpShort(byte* data);
  int JumpConditional(byte* data, const char* comment);
  int JumpConditionalShort(byte* data, const char* comment);
334
  int SetCC(byte* data);
335
  int CMov(byte* data);
336
  int FPUInstruction(byte* data);
337 338
  int MemoryFPUInstruction(int escape_opcode, int regop, byte* modrm_start);
  int RegisterFPUInstruction(int escape_opcode, byte modrm_byte);
339 340 341 342 343 344 345 346 347 348 349 350 351 352
  void AppendToBuffer(const char* format, ...);


  void UnimplementedInstruction() {
    if (abort_on_unimplemented_) {
      UNIMPLEMENTED();
    } else {
      AppendToBuffer("'Unimplemented Instruction'");
    }
  }
};


void DisassemblerIA32::AppendToBuffer(const char* format, ...) {
353
  v8::internal::Vector<char> buf = tmp_buffer_ + tmp_buffer_pos_;
354 355
  va_list args;
  va_start(args, format);
356
  int result = v8::internal::OS::VSNPrintF(buf, format, args);
357 358 359 360
  va_end(args);
  tmp_buffer_pos_ += result;
}

361 362 363
int DisassemblerIA32::PrintRightOperandHelper(
    byte* modrmp,
    RegisterNameMapping register_name) {
364 365 366 367 368 369 370 371 372 373 374 375 376
  int mod, regop, rm;
  get_modrm(*modrmp, &mod, &regop, &rm);
  switch (mod) {
    case 0:
      if (rm == ebp) {
        int32_t disp = *reinterpret_cast<int32_t*>(modrmp+1);
        AppendToBuffer("[0x%x]", disp);
        return 5;
      } else if (rm == esp) {
        byte sib = *(modrmp + 1);
        int scale, index, base;
        get_sib(sib, &scale, &index, &base);
        if (index == esp && base == esp && scale == 0 /*times_1*/) {
377
          AppendToBuffer("[%s]", (this->*register_name)(rm));
378 379 380 381
          return 2;
        } else if (base == ebp) {
          int32_t disp = *reinterpret_cast<int32_t*>(modrmp + 2);
          AppendToBuffer("[%s*%d+0x%x]",
382
                         (this->*register_name)(index),
383 384 385 386 387 388
                         1 << scale,
                         disp);
          return 6;
        } else if (index != esp && base != ebp) {
          // [base+index*scale]
          AppendToBuffer("[%s+%s*%d]",
389 390
                         (this->*register_name)(base),
                         (this->*register_name)(index),
391 392 393 394 395 396 397
                         1 << scale);
          return 2;
        } else {
          UnimplementedInstruction();
          return 1;
        }
      } else {
398
        AppendToBuffer("[%s]", (this->*register_name)(rm));
399 400 401 402 403 404 405 406 407 408 409 410
        return 1;
      }
      break;
    case 1:  // fall through
    case 2:
      if (rm == esp) {
        byte sib = *(modrmp + 1);
        int scale, index, base;
        get_sib(sib, &scale, &index, &base);
        int disp =
            mod == 2 ? *reinterpret_cast<int32_t*>(modrmp + 2) : *(modrmp + 2);
        if (index == base && index == rm /*esp*/ && scale == 0 /*times_1*/) {
411
          AppendToBuffer("[%s+0x%x]", (this->*register_name)(rm), disp);
412 413
        } else {
          AppendToBuffer("[%s+%s*%d+0x%x]",
414 415
                         (this->*register_name)(base),
                         (this->*register_name)(index),
416 417 418 419 420 421 422 423
                         1 << scale,
                         disp);
        }
        return mod == 2 ? 6 : 3;
      } else {
        // No sib.
        int disp =
            mod == 2 ? *reinterpret_cast<int32_t*>(modrmp + 1) : *(modrmp + 1);
424
        AppendToBuffer("[%s+0x%x]", (this->*register_name)(rm), disp);
425 426 427 428
        return mod == 2 ? 5 : 2;
      }
      break;
    case 3:
429
      AppendToBuffer("%s", (this->*register_name)(rm));
430 431 432 433 434 435 436 437 438
      return 1;
    default:
      UnimplementedInstruction();
      return 1;
  }
  UNREACHABLE();
}


439 440 441 442 443 444 445 446 447 448 449
int DisassemblerIA32::PrintRightOperand(byte* modrmp) {
  return PrintRightOperandHelper(modrmp, &DisassemblerIA32::NameOfCPURegister);
}


int DisassemblerIA32::PrintRightByteOperand(byte* modrmp) {
  return PrintRightOperandHelper(modrmp,
                                 &DisassemblerIA32::NameOfByteCPURegister);
}


450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510
// Returns number of bytes used including the current *data.
// Writes instruction's mnemonic, left and right operands to 'tmp_buffer_'.
int DisassemblerIA32::PrintOperands(const char* mnem,
                                    OperandOrder op_order,
                                    byte* data) {
  byte modrm = *data;
  int mod, regop, rm;
  get_modrm(modrm, &mod, &regop, &rm);
  int advance = 0;
  switch (op_order) {
    case REG_OPER_OP_ORDER: {
      AppendToBuffer("%s %s,", mnem, NameOfCPURegister(regop));
      advance = PrintRightOperand(data);
      break;
    }
    case OPER_REG_OP_ORDER: {
      AppendToBuffer("%s ", mnem);
      advance = PrintRightOperand(data);
      AppendToBuffer(",%s", NameOfCPURegister(regop));
      break;
    }
    default:
      UNREACHABLE();
      break;
  }
  return advance;
}


// Returns number of bytes used by machine instruction, including *data byte.
// Writes immediate instructions to 'tmp_buffer_'.
int DisassemblerIA32::PrintImmediateOp(byte* data) {
  bool sign_extension_bit = (*data & 0x02) != 0;
  byte modrm = *(data+1);
  int mod, regop, rm;
  get_modrm(modrm, &mod, &regop, &rm);
  const char* mnem = "Imm???";
  switch (regop) {
    case 0: mnem = "add"; break;
    case 1: mnem = "or"; break;
    case 2: mnem = "adc"; break;
    case 4: mnem = "and"; break;
    case 5: mnem = "sub"; break;
    case 6: mnem = "xor"; break;
    case 7: mnem = "cmp"; break;
    default: UnimplementedInstruction();
  }
  AppendToBuffer("%s ", mnem);
  int count = PrintRightOperand(data+1);
  if (sign_extension_bit) {
    AppendToBuffer(",0x%x", *(data + 1 + count));
    return 1 + count + 1 /*int8*/;
  } else {
    AppendToBuffer(",0x%x", *reinterpret_cast<int32_t*>(data + 1 + count));
    return 1 + count + 4 /*int32_t*/;
  }
}


// Returns number of bytes used, including *data.
int DisassemblerIA32::F7Instruction(byte* data) {
511
  ASSERT_EQ(0xF7, *data);
512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543
  byte modrm = *(data+1);
  int mod, regop, rm;
  get_modrm(modrm, &mod, &regop, &rm);
  if (mod == 3 && regop != 0) {
    const char* mnem = NULL;
    switch (regop) {
      case 2: mnem = "not"; break;
      case 3: mnem = "neg"; break;
      case 4: mnem = "mul"; break;
      case 7: mnem = "idiv"; break;
      default: UnimplementedInstruction();
    }
    AppendToBuffer("%s %s", mnem, NameOfCPURegister(rm));
    return 2;
  } else if (mod == 3 && regop == eax) {
    int32_t imm = *reinterpret_cast<int32_t*>(data+2);
    AppendToBuffer("test %s,0x%x", NameOfCPURegister(rm), imm);
    return 6;
  } else if (regop == eax) {
    AppendToBuffer("test ");
    int count = PrintRightOperand(data+1);
    int32_t imm = *reinterpret_cast<int32_t*>(data+1+count);
    AppendToBuffer(",0x%x", imm);
    return 1+count+4 /*int32_t*/;
  } else {
    UnimplementedInstruction();
    return 2;
  }
}

int DisassemblerIA32::D1D3C1Instruction(byte* data) {
  byte op = *data;
544
  ASSERT(op == 0xD1 || op == 0xD3 || op == 0xC1);
545 546 547 548 549 550 551
  byte modrm = *(data+1);
  int mod, regop, rm;
  get_modrm(modrm, &mod, &regop, &rm);
  int imm8 = -1;
  int num_bytes = 2;
  if (mod == 3) {
    const char* mnem = NULL;
552 553 554 555 556 557 558 559 560
    switch (regop) {
      case kROL: mnem = "rol"; break;
      case kROR: mnem = "ror"; break;
      case kRCL: mnem = "rcl"; break;
      case kSHL: mnem = "shl"; break;
      case KSHR: mnem = "shr"; break;
      case kSAR: mnem = "sar"; break;
      default: UnimplementedInstruction();
    }
561 562 563 564 565 566
    if (op == 0xD1) {
      imm8 = 1;
    } else if (op == 0xC1) {
      imm8 = *(data+2);
      num_bytes = 3;
    } else if (op == 0xD3) {
567
      // Shift/rotate by cl.
568
    }
569
    ASSERT_NE(NULL, mnem);
570 571 572 573 574 575 576 577 578 579 580 581 582 583 584
    AppendToBuffer("%s %s,", mnem, NameOfCPURegister(rm));
    if (imm8 > 0) {
      AppendToBuffer("%d", imm8);
    } else {
      AppendToBuffer("cl");
    }
  } else {
    UnimplementedInstruction();
  }
  return num_bytes;
}


// Returns number of bytes used, including *data.
int DisassemblerIA32::JumpShort(byte* data) {
585
  ASSERT_EQ(0xEB, *data);
586 587 588 589 590 591 592 593 594
  byte b = *(data+1);
  byte* dest = data + static_cast<int8_t>(b) + 2;
  AppendToBuffer("jmp %s", NameOfAddress(dest));
  return 2;
}


// Returns number of bytes used, including *data.
int DisassemblerIA32::JumpConditional(byte* data, const char* comment) {
595
  ASSERT_EQ(0x0F, *data);
596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620
  byte cond = *(data+1) & 0x0F;
  byte* dest = data + *reinterpret_cast<int32_t*>(data+2) + 6;
  const char* mnem = jump_conditional_mnem[cond];
  AppendToBuffer("%s %s", mnem, NameOfAddress(dest));
  if (comment != NULL) {
    AppendToBuffer(", %s", comment);
  }
  return 6;  // includes 0x0F
}


// Returns number of bytes used, including *data.
int DisassemblerIA32::JumpConditionalShort(byte* data, const char* comment) {
  byte cond = *data & 0x0F;
  byte b = *(data+1);
  byte* dest = data + static_cast<int8_t>(b) + 2;
  const char* mnem = jump_conditional_mnem[cond];
  AppendToBuffer("%s %s", mnem, NameOfAddress(dest));
  if (comment != NULL) {
    AppendToBuffer(", %s", comment);
  }
  return 2;
}


621 622
// Returns number of bytes used, including *data.
int DisassemblerIA32::SetCC(byte* data) {
623
  ASSERT_EQ(0x0F, *data);
624 625 626 627
  byte cond = *(data+1) & 0x0F;
  const char* mnem = set_conditional_mnem[cond];
  AppendToBuffer("%s ", mnem);
  PrintRightByteOperand(data+2);
628
  return 3;  // Includes 0x0F.
629 630 631
}


632 633
// Returns number of bytes used, including *data.
int DisassemblerIA32::CMov(byte* data) {
634
  ASSERT_EQ(0x0F, *data);
635 636 637 638 639 640 641
  byte cond = *(data + 1) & 0x0F;
  const char* mnem = conditional_move_mnem[cond];
  int op_size = PrintOperands(mnem, REG_OPER_OP_ORDER, data + 2);
  return 2 + op_size;  // includes 0x0F
}


642 643
// Returns number of bytes used, including *data.
int DisassemblerIA32::FPUInstruction(byte* data) {
644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664
  byte escape_opcode = *data;
  ASSERT_EQ(0xD8, escape_opcode & 0xF8);
  byte modrm_byte = *(data+1);

  if (modrm_byte >= 0xC0) {
    return RegisterFPUInstruction(escape_opcode, modrm_byte);
  } else {
    return MemoryFPUInstruction(escape_opcode, modrm_byte, data+1);
  }
}

int DisassemblerIA32::MemoryFPUInstruction(int escape_opcode,
                                           int modrm_byte,
                                           byte* modrm_start) {
  const char* mnem = "?";
  int regop = (modrm_byte >> 3) & 0x7;  // reg/op field of modrm byte.
  switch (escape_opcode) {
    case 0xD9: switch (regop) {
        case 0: mnem = "fld_s"; break;
        case 3: mnem = "fstp_s"; break;
        case 7: mnem = "fstcw"; break;
665 666
        default: UnimplementedInstruction();
      }
667 668 669 670 671 672 673
      break;

    case 0xDB: switch (regop) {
        case 0: mnem = "fild_s"; break;
        case 1: mnem = "fisttp_s"; break;
        case 2: mnem = "fist_s"; break;
        case 3: mnem = "fistp_s"; break;
674 675
        default: UnimplementedInstruction();
      }
676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800
      break;

    case 0xDD: switch (regop) {
        case 0: mnem = "fld_d"; break;
        case 3: mnem = "fstp_d"; break;
        default: UnimplementedInstruction();
      }
      break;

    case 0xDF: switch (regop) {
        case 5: mnem = "fild_d"; break;
        case 7: mnem = "fistp_d"; break;
        default: UnimplementedInstruction();
      }
      break;

    default: UnimplementedInstruction();
  }
  AppendToBuffer("%s ", mnem);
  int count = PrintRightOperand(modrm_start);
  return count + 1;
}

int DisassemblerIA32::RegisterFPUInstruction(int escape_opcode,
                                             byte modrm_byte) {
  bool has_register = false;  // Is the FPU register encoded in modrm_byte?
  const char* mnem = "?";

  switch (escape_opcode) {
    case 0xD8:
      UnimplementedInstruction();
      break;

    case 0xD9:
      switch (modrm_byte & 0xF8) {
        case 0xC8:
          mnem = "fxch";
          has_register = true;
          break;
        default:
          switch (modrm_byte) {
            case 0xE0: mnem = "fchs"; break;
            case 0xE1: mnem = "fabs"; break;
            case 0xE4: mnem = "ftst"; break;
            case 0xE8: mnem = "fld1"; break;
            case 0xEE: mnem = "fldz"; break;
            case 0xF5: mnem = "fprem1"; break;
            case 0xF7: mnem = "fincstp"; break;
            case 0xF8: mnem = "fprem"; break;
            case 0xFE: mnem = "fsin"; break;
            case 0xFF: mnem = "fcos"; break;
            default: UnimplementedInstruction();
          }
      }
      break;

    case 0xDA:
      if (modrm_byte == 0xE9) {
        mnem = "fucompp";
      } else {
        UnimplementedInstruction();
      }
      break;

    case 0xDB:
      if ((modrm_byte & 0xF8) == 0xE8) {
        mnem = "fucomi";
        has_register = true;
      } else if (modrm_byte  == 0xE2) {
        mnem = "fclex";
      } else {
        UnimplementedInstruction();
      }
      break;

    case 0xDC:
      has_register = true;
      switch (modrm_byte & 0xF8) {
        case 0xC0: mnem = "fadd"; break;
        case 0xE8: mnem = "fsub"; break;
        case 0xC8: mnem = "fmul"; break;
        case 0xF8: mnem = "fdiv"; break;
        default: UnimplementedInstruction();
      }
      break;

    case 0xDD:
      has_register = true;
      switch (modrm_byte & 0xF8) {
        case 0xC0: mnem = "ffree"; break;
        case 0xD8: mnem = "fstp"; break;
        default: UnimplementedInstruction();
      }
      break;

    case 0xDE:
      if (modrm_byte  == 0xD9) {
        mnem = "fcompp";
      } else {
        has_register = true;
        switch (modrm_byte & 0xF8) {
          case 0xC0: mnem = "faddp"; break;
          case 0xE8: mnem = "fsubp"; break;
          case 0xC8: mnem = "fmulp"; break;
          case 0xF8: mnem = "fdivp"; break;
          default: UnimplementedInstruction();
        }
      }
      break;

    case 0xDF:
      if (modrm_byte == 0xE0) {
        mnem = "fnstsw_ax";
      } else if ((modrm_byte & 0xF8) == 0xE8) {
        mnem = "fucomip";
        has_register = true;
      }
      break;

    default: UnimplementedInstruction();
  }

  if (has_register) {
    AppendToBuffer("%s st%d", mnem, modrm_byte & 0x7);
  } else {
801
    AppendToBuffer("%s", mnem);
802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825
  }
  return 2;
}


// Mnemonics for instructions 0xF0 byte.
// Returns NULL if the instruction is not handled here.
static const char* F0Mnem(byte f0byte) {
  switch (f0byte) {
    case 0xA2: return "cpuid";
    case 0x31: return "rdtsc";
    case 0xBE: return "movsx_b";
    case 0xBF: return "movsx_w";
    case 0xB6: return "movzx_b";
    case 0xB7: return "movzx_w";
    case 0xAF: return "imul";
    case 0xA5: return "shld";
    case 0xAD: return "shrd";
    case 0xAB: return "bts";
    default: return NULL;
  }
}


826
// Disassembled instruction '*instr' and writes it into 'out_buffer'.
827
int DisassemblerIA32::InstructionDecode(v8::internal::Vector<char> out_buffer,
828 829 830 831 832
                                        byte* instr) {
  tmp_buffer_pos_ = 0;  // starting to write as position 0
  byte* data = instr;
  // Check for hints.
  const char* branch_hint = NULL;
833
  // We use these two prefixes only with branch prediction
834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944
  if (*data == 0x3E /*ds*/) {
    branch_hint = "predicted taken";
    data++;
  } else if (*data == 0x2E /*cs*/) {
    branch_hint = "predicted not taken";
    data++;
  }
  bool processed = true;  // Will be set to false if the current instruction
                          // is not in 'instructions' table.
  const InstructionDesc& idesc = instruction_table.Get(*data);
  switch (idesc.type) {
    case ZERO_OPERANDS_INSTR:
      AppendToBuffer(idesc.mnem);
      data++;
      break;

    case TWO_OPERANDS_INSTR:
      data++;
      data += PrintOperands(idesc.mnem, idesc.op_order_, data);
      break;

    case JUMP_CONDITIONAL_SHORT_INSTR:
      data += JumpConditionalShort(data, branch_hint);
      break;

    case REGISTER_INSTR:
      AppendToBuffer("%s %s", idesc.mnem, NameOfCPURegister(*data & 0x07));
      data++;
      break;

    case MOVE_REG_INSTR: {
      byte* addr = reinterpret_cast<byte*>(*reinterpret_cast<int32_t*>(data+1));
      AppendToBuffer("mov %s,%s",
                     NameOfCPURegister(*data & 0x07),
                     NameOfAddress(addr));
      data += 5;
      break;
    }

    case CALL_JUMP_INSTR: {
      byte* addr = data + *reinterpret_cast<int32_t*>(data+1) + 5;
      AppendToBuffer("%s %s", idesc.mnem, NameOfAddress(addr));
      data += 5;
      break;
    }

    case SHORT_IMMEDIATE_INSTR: {
      byte* addr = reinterpret_cast<byte*>(*reinterpret_cast<int32_t*>(data+1));
      AppendToBuffer("%s eax, %s", idesc.mnem, NameOfAddress(addr));
      data += 5;
      break;
    }

    case NO_INSTR:
      processed = false;
      break;

    default:
      UNIMPLEMENTED();  // This type is not implemented.
  }
  //----------------------------
  if (!processed) {
    switch (*data) {
      case 0xC2:
        AppendToBuffer("ret 0x%x", *reinterpret_cast<uint16_t*>(data+1));
        data += 3;
        break;

      case 0x69:  // fall through
      case 0x6B:
        { int mod, regop, rm;
          get_modrm(*(data+1), &mod, &regop, &rm);
          int32_t imm =
              *data == 0x6B ? *(data+2) : *reinterpret_cast<int32_t*>(data+2);
          AppendToBuffer("imul %s,%s,0x%x",
                         NameOfCPURegister(regop),
                         NameOfCPURegister(rm),
                         imm);
          data += 2 + (*data == 0x6B ? 1 : 4);
        }
        break;

      case 0xF6:
        { int mod, regop, rm;
          get_modrm(*(data+1), &mod, &regop, &rm);
          if (mod == 3 && regop == eax) {
            AppendToBuffer("test_b %s,%d", NameOfCPURegister(rm), *(data+2));
          } else {
            UnimplementedInstruction();
          }
          data += 3;
        }
        break;

      case 0x81:  // fall through
      case 0x83:  // 0x81 with sign extension bit set
        data += PrintImmediateOp(data);
        break;

      case 0x0F:
        { byte f0byte = *(data+1);
          const char* f0mnem = F0Mnem(f0byte);
          if (f0byte == 0xA2 || f0byte == 0x31) {
            AppendToBuffer("%s", f0mnem);
            data += 2;
          } else if ((f0byte & 0xF0) == 0x80) {
            data += JumpConditional(data, branch_hint);
          } else if (f0byte == 0xBE || f0byte == 0xBF || f0byte == 0xB6 ||
                     f0byte == 0xB7 || f0byte == 0xAF) {
            data += 2;
            data += PrintOperands(f0mnem, REG_OPER_OP_ORDER, data);
945 946
          } else if ((f0byte & 0xF0) == 0x90) {
            data += SetCC(data);
947 948
          } else if ((f0byte & 0xF0) == 0x40) {
            data += CMov(data);
949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987
          } else {
            data += 2;
            if (f0byte == 0xAB || f0byte == 0xA5 || f0byte == 0xAD) {
              // shrd, shld, bts
              AppendToBuffer("%s ", f0mnem);
              int mod, regop, rm;
              get_modrm(*data, &mod, &regop, &rm);
              data += PrintRightOperand(data);
              if (f0byte == 0xAB) {
                AppendToBuffer(",%s", NameOfCPURegister(regop));
              } else {
                AppendToBuffer(",%s,cl", NameOfCPURegister(regop));
              }
            } else {
              UnimplementedInstruction();
            }
          }
        }
        break;

      case 0x8F:
        { data++;
          int mod, regop, rm;
          get_modrm(*data, &mod, &regop, &rm);
          if (regop == eax) {
            AppendToBuffer("pop ");
            data += PrintRightOperand(data);
          }
        }
        break;

      case 0xFF:
        { data++;
          int mod, regop, rm;
          get_modrm(*data, &mod, &regop, &rm);
          const char* mnem = NULL;
          switch (regop) {
            case esi: mnem = "push"; break;
            case eax: mnem = "inc"; break;
lrn@chromium.org's avatar
lrn@chromium.org committed
988
            case ecx: mnem = "dec"; break;
989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009
            case edx: mnem = "call"; break;
            case esp: mnem = "jmp"; break;
            default: mnem = "???";
          }
          AppendToBuffer("%s ", mnem);
          data += PrintRightOperand(data);
        }
        break;

      case 0xC7:  // imm32, fall through
      case 0xC6:  // imm8
        { bool is_byte = *data == 0xC6;
          data++;
          AppendToBuffer("%s ", is_byte ? "mov_b" : "mov");
          data += PrintRightOperand(data);
          int32_t imm = is_byte ? *data : *reinterpret_cast<int32_t*>(data);
          AppendToBuffer(",0x%x", imm);
          data += is_byte ? 1 : 4;
        }
        break;

1010 1011
      case 0x80:
        { data++;
1012 1013 1014 1015 1016 1017 1018 1019 1020 1021
          int mod, regop, rm;
          get_modrm(*data, &mod, &regop, &rm);
          const char* mnem = NULL;
          printf("%d\n", regop);
          switch (regop) {
            case 5:  mnem = "subb"; break;
            case 7:  mnem = "cmpb"; break;
            default: UnimplementedInstruction();
          }
          AppendToBuffer("%s ", mnem);
1022 1023 1024 1025 1026 1027 1028
          data += PrintRightOperand(data);
          int32_t imm = *data;
          AppendToBuffer(",0x%x", imm);
          data++;
        }
        break;

1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052
      case 0x88:  // 8bit, fall through
      case 0x89:  // 32bit
        { bool is_byte = *data == 0x88;
          int mod, regop, rm;
          data++;
          get_modrm(*data, &mod, &regop, &rm);
          AppendToBuffer("%s ", is_byte ? "mov_b" : "mov");
          data += PrintRightOperand(data);
          AppendToBuffer(",%s", NameOfCPURegister(regop));
        }
        break;

      case 0x66:  // prefix
        data++;
        if (*data == 0x8B) {
          data++;
          data += PrintOperands("mov_w", REG_OPER_OP_ORDER, data);
        } else if (*data == 0x89) {
          data++;
          int mod, regop, rm;
          get_modrm(*data, &mod, &regop, &rm);
          AppendToBuffer("mov_w ");
          data += PrintRightOperand(data);
          AppendToBuffer(",%s", NameOfCPURegister(regop));
1053 1054 1055 1056 1057 1058 1059 1060 1061 1062
        } else if (*data == 0x0F) {
          data++;
          if (*data == 0x2F) {
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("comisd %s,%s",
                           NameOfXMMRegister(regop),
                           NameOfXMMRegister(rm));
            data++;
bak@chromium.org's avatar
bak@chromium.org committed
1063
          } else if (*data == 0x57) {
1064 1065 1066 1067 1068 1069 1070
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("xorpd %s,%s",
                           NameOfXMMRegister(regop),
                           NameOfXMMRegister(rm));
            data++;
1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083
          } else if (*data == 0x6F) {
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("movdqa %s,", NameOfXMMRegister(regop));
            data += PrintRightOperand(data);
          } else if (*data == 0x7F) {
            AppendToBuffer("movdqa ");
            data++;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            data += PrintRightOperand(data);
            AppendToBuffer(",%s", NameOfXMMRegister(regop));
1084 1085 1086
          } else {
            UnimplementedInstruction();
          }
1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119
        } else {
          UnimplementedInstruction();
        }
        break;

      case 0xFE:
        { data++;
          int mod, regop, rm;
          get_modrm(*data, &mod, &regop, &rm);
          if (mod == 3 && regop == ecx) {
            AppendToBuffer("dec_b %s", NameOfCPURegister(rm));
          } else {
            UnimplementedInstruction();
          }
          data++;
        }
        break;

      case 0x68:
        AppendToBuffer("push 0x%x", *reinterpret_cast<int32_t*>(data+1));
        data += 5;
        break;

      case 0x6A:
        AppendToBuffer("push 0x%x", *reinterpret_cast<int8_t*>(data + 1));
        data += 2;
        break;

      case 0xA8:
        AppendToBuffer("test al,0x%x", *reinterpret_cast<uint8_t*>(data+1));
        data += 2;
        break;

1120 1121 1122 1123 1124
      case 0x2C:
        AppendToBuffer("subb eax,0x%x", *reinterpret_cast<uint8_t*>(data+1));
        data += 2;
        break;

1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136
      case 0xA9:
        AppendToBuffer("test eax,0x%x", *reinterpret_cast<int32_t*>(data+1));
        data += 5;
        break;

      case 0xD1:  // fall through
      case 0xD3:  // fall through
      case 0xC1:
        data += D1D3C1Instruction(data);
        break;

      case 0xD9:  // fall through
1137
      case 0xDA:  // fall through
1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194
      case 0xDB:  // fall through
      case 0xDC:  // fall through
      case 0xDD:  // fall through
      case 0xDE:  // fall through
      case 0xDF:
        data += FPUInstruction(data);
        break;

      case 0xEB:
        data += JumpShort(data);
        break;

      case 0xF2:
        if (*(data+1) == 0x0F) {
          byte b2 = *(data+2);
          if (b2 == 0x11) {
            AppendToBuffer("movsd ");
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            data += PrintRightOperand(data);
            AppendToBuffer(",%s", NameOfXMMRegister(regop));
          } else if (b2 == 0x10) {
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("movsd %s,", NameOfXMMRegister(regop));
            data += PrintRightOperand(data);
          } else {
            const char* mnem = "?";
            switch (b2) {
              case 0x2A: mnem = "cvtsi2sd"; break;
              case 0x58: mnem = "addsd"; break;
              case 0x59: mnem = "mulsd"; break;
              case 0x5C: mnem = "subsd"; break;
              case 0x5E: mnem = "divsd"; break;
            }
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            if (b2 == 0x2A) {
              AppendToBuffer("%s %s,", mnem, NameOfXMMRegister(regop));
              data += PrintRightOperand(data);
            } else {
              AppendToBuffer("%s %s,%s",
                             mnem,
                             NameOfXMMRegister(regop),
                             NameOfXMMRegister(rm));
              data++;
            }
          }
        } else {
          UnimplementedInstruction();
        }
        break;

      case 0xF3:
1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217
        if (*(data+1) == 0x0F) {
          if (*(data+2) == 0x2C) {
            data += 3;
            data += PrintOperands("cvttss2si", REG_OPER_OP_ORDER, data);
          } else  if (*(data+2) == 0x6F) {
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            AppendToBuffer("movdqu %s,", NameOfXMMRegister(regop));
            data += PrintRightOperand(data);
          } else  if (*(data+2) == 0x7F) {
            AppendToBuffer("movdqu ");
            data += 3;
            int mod, regop, rm;
            get_modrm(*data, &mod, &regop, &rm);
            data += PrintRightOperand(data);
            AppendToBuffer(",%s", NameOfXMMRegister(regop));
          } else {
            UnimplementedInstruction();
          }
        } else if (*(data+1) == 0xA5) {
          data += 2;
          AppendToBuffer("rep_movs");
1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236
        } else {
          UnimplementedInstruction();
        }
        break;

      case 0xF7:
        data += F7Instruction(data);
        break;

      default:
        UnimplementedInstruction();
    }
  }

  if (tmp_buffer_pos_ < sizeof tmp_buffer_) {
    tmp_buffer_[tmp_buffer_pos_] = '\0';
  }

  int instr_len = data - instr;
1237 1238 1239
  if (instr_len == 0) {
    printf("%02x", *data);
  }
1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255
  ASSERT(instr_len > 0);  // Ensure progress.

  int outp = 0;
  // Instruction bytes.
  for (byte* bp = instr; bp < data; bp++) {
    outp += v8::internal::OS::SNPrintF(out_buffer + outp,
                                       "%02x",
                                       *bp);
  }
  for (int i = 6 - instr_len; i >= 0; i--) {
    outp += v8::internal::OS::SNPrintF(out_buffer + outp,
                                       "  ");
  }

  outp += v8::internal::OS::SNPrintF(out_buffer + outp,
                                     " %s",
1256
                                     tmp_buffer_.start());
1257 1258 1259 1260 1261 1262 1263 1264
  return instr_len;
}


//------------------------------------------------------------------------------


static const char* cpu_regs[8] = {
1265 1266 1267 1268 1269 1270
  "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi"
};


static const char* byte_cpu_regs[8] = {
  "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh"
1271 1272 1273 1274
};


static const char* xmm_regs[8] = {
1275
  "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7"
1276 1277 1278 1279
};


const char* NameConverter::NameOfAddress(byte* addr) const {
1280
  static v8::internal::EmbeddedVector<char, 32> tmp_buffer;
1281 1282
  v8::internal::OS::SNPrintF(tmp_buffer, "%p", addr);
  return tmp_buffer.start();
1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296
}


const char* NameConverter::NameOfConstant(byte* addr) const {
  return NameOfAddress(addr);
}


const char* NameConverter::NameOfCPURegister(int reg) const {
  if (0 <= reg && reg < 8) return cpu_regs[reg];
  return "noreg";
}


1297 1298 1299 1300 1301 1302
const char* NameConverter::NameOfByteCPURegister(int reg) const {
  if (0 <= reg && reg < 8) return byte_cpu_regs[reg];
  return "noreg";
}


1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324
const char* NameConverter::NameOfXMMRegister(int reg) const {
  if (0 <= reg && reg < 8) return xmm_regs[reg];
  return "noxmmreg";
}


const char* NameConverter::NameInCode(byte* addr) const {
  // IA32 does not embed debug strings at the moment.
  UNREACHABLE();
  return "";
}


//------------------------------------------------------------------------------

Disassembler::Disassembler(const NameConverter& converter)
    : converter_(converter) {}


Disassembler::~Disassembler() {}


1325
int Disassembler::InstructionDecode(v8::internal::Vector<char> buffer,
1326 1327
                                    byte* instruction) {
  DisassemblerIA32 d(converter_, false /*do not crash if unimplemented*/);
1328
  return d.InstructionDecode(buffer, instruction);
1329 1330 1331
}


1332 1333 1334 1335
// The IA-32 assembler does not currently use constant pools.
int Disassembler::ConstantPoolSizeAt(byte* instruction) { return -1; }


1336
/*static*/ void Disassembler::Disassemble(FILE* f, byte* begin, byte* end) {
1337 1338
  NameConverter converter;
  Disassembler d(converter);
1339
  for (byte* pc = begin; pc < end;) {
1340
    v8::internal::EmbeddedVector<char, 128> buffer;
1341 1342
    buffer[0] = '\0';
    byte* prev_pc = pc;
1343
    pc += d.InstructionDecode(buffer, pc);
1344 1345 1346 1347 1348 1349 1350 1351 1352
    fprintf(f, "%p", prev_pc);
    fprintf(f, "    ");

    for (byte* bp = prev_pc; bp < pc; bp++) {
      fprintf(f, "%02x",  *bp);
    }
    for (int i = 6 - (pc - prev_pc); i >= 0; i--) {
      fprintf(f, "  ");
    }
1353
    fprintf(f, "  %s\n", buffer.start());
1354 1355 1356 1357 1358
  }
}


}  // namespace disasm