This is a follow up change to https://crrev.com/c/2499294.

SSE instructions require memory operands to be 16-byte aligned, which we
cannot guarantee yet. So we force the operands to be registers in the
instruction selector.

AVX instructiosn (VEX-encoded) support unaligned memory operands, but
can have performance reductions if it crosses cache lines. For
simplicity we also force the operands to be registers.

In the codegen we can remove the case where the operand is not a
register, and also for SSE assert that dst == src.

Bug: v8:9198
Change-Id: Ibee33896dc9cc4e97d792c5b7bdf5e66ce34de9c
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2500924Reviewed-by: Bill Budge <bbudge@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#70814}