- 22 Feb, 2022 1 commit
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Yuxiang Cao authored
Implement vector widening floating-point instructions: add/subtract/multiply/multiply-add/reduction instructions, eg. `vfwadd.vf`, `vfwmacc.vf`, `vfwredosum.vs`. Add tests and simulator support for all newly added instructions. Bug: v8:11976 Change-Id: I0909eeab24ba075c5a21743bb49538f154ce8aa2 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3442257Reviewed-by:
ji qiu <qiuji@iscas.ac.cn> Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Commit-Queue: Yahan Lu <yahan@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#79205}
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- 10 Jan, 2022 1 commit
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Yujie Wang authored
- Implement `kRiscvF32x4RecipApprox`, `kRiscvF32x4RecipSqrtApprox`, `kRiscvF32x4Qfma`, `kRiscvF32x4Qfms`, `kRiscvF64x2Qfma` and `kRiscvF64x2Qfms` in `code-generator-riscv64.cc` - Reuse lane-select, min-max and trunc instrctions in `instruction-selector-riscv64.cc` Bug: v8:11976 Change-Id: I8566f7e082a3d7071ec9fc64c742da82425a4d4d Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3364077Reviewed-by:
Yahan Lu <yahan@iscas.ac.cn> Reviewed-by:
Clemens Backes <clemensb@chromium.org> Reviewed-by:
Tobias Tebbi <tebbi@chromium.org> Cr-Commit-Position: refs/heads/main@{#78524}
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- 08 Dec, 2021 1 commit
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Lu Yahan authored
Add func UseImmediate64(int64_t imm) into instruction-selector-impl Bug: v8:11976 Change-Id: I274ab59cc6d9a9cdc8b4081a7c418c56c3e8f5b7 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3312453Reviewed-by:
ji qiu <qiuji@iscas.ac.cn> Reviewed-by:
Maya Lekova <mslekova@chromium.org> Commit-Queue: Yahan Lu <yahan@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#78288}
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- 25 Nov, 2021 1 commit
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Lu Yahan authored
Bug: v8:11976 Change-Id: Ifdce8e668c4b0fe20180c8d28b9c1d4abe705a67 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3297354 Commit-Queue: ji qiu <qiuji@iscas.ac.cn> Reviewed-by:
ji qiu <qiuji@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#78078}
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- 12 Nov, 2021 1 commit
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Yujie Wang authored
- Add Wasm SIMD packing instruction: `LiftoffAssembler::emit_i8x16_{s,u}convert_i16x8` - Add Wasm SIMD unpacking instructions: `LiftoffAssembler::emit_i64x2_{s,u}convert_i32x4_{low,high}` `LiftoffAssembler::emit_i32x4_{s,u}convert_i16x8_{low,high}` `LiftoffAssembler::emit_i64x2_{s,u}convert_i32x4_{low,high}` - Add RVV instrucions: `vzext_vf{2,4,8}` and `vsext_vf{2,4,8}` - Fixed simulator for `vslidedown_vi` Bug: v8:11976 Change-Id: Idd383bc566589ce183f4fcef2201d2ccfe03519f Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3273812Reviewed-by:
ji qiu <qiuji@iscas.ac.cn> Reviewed-by:
Yahan Lu <yahan@iscas.ac.cn> Commit-Queue: ji qiu <qiuji@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#77865}
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- 28 Oct, 2021 1 commit
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Yujie Wang authored
Implement `LiftoffAssembler::emit_i16x8_sconvert_i32x4` for riscv. Add tests for rvv integer and floating-point instructions. Add simulator support for rvv instructions, e.g. `vfmadd`, `vnclip`. Fixed order of operands for `vfdiv.vv`. Bug: v8:11976 Change-Id: I0691ac66771468533c5994be1fc8a86b09d3c738 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3225319Reviewed-by:
Yahan Lu <yahan@iscas.ac.cn> Reviewed-by:
Michael Lippautz <mlippautz@chromium.org> Commit-Queue: Yahan Lu <yahan@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#77595}
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- 15 Sep, 2021 1 commit
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Lu Yahan authored
Bug: v8:11976 Change-Id: I19e1ef43f073c8155dbc2890de0f331782eb7aac Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3156588 Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn> Reviewed-by:
Ji Qiu <qiuji@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#76835}
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- 13 Sep, 2021 1 commit
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Lu Yahan authored
In riscv64, pc-relatice call need meet IsInt32(offset + 0x800), so max pcrelatice code range is 4094MB. Change-Id: Id3481483eb3131b5c08f22bde08206ee30cc25db Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3156585 Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn> Reviewed-by:
Ji Qiu <qiuji@iscas.ac.cn> Cr-Commit-Position: refs/heads/main@{#76794}
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- 07 Sep, 2021 1 commit
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Lu Yahan authored
- Add vsetivli/I8x16Add/vl/vse8 - In Rvv, Vector regs is different from Float Regs. But in this cl, in order to facilitate modification, it is assumed that the vector register and float register share a set of register codes. - Because v0 is mask reg, we can't allocate it . And transfer float into vector reg, so i delete ft0 from AllocateReg. Bug: v8:11976 Change-Id: I66185d1f5ead985489bcbdf671b131f02a6bd7c2 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3005768 Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn> Reviewed-by:
Thibaud Michaud <thibaudm@chromium.org> Reviewed-by:
Ji Qiu <qiuji@iscas.ac.cn> Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Cr-Commit-Position: refs/heads/main@{#76700}
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- 06 Aug, 2021 1 commit
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Derek Tu authored
Lets the macro-assembler compile RISC-V C-Extension instructions when the corresponding flag is set during runtime. Change-Id: I443d026653b9945ac7ccff41b0ca3f7db9b65775 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3039384Reviewed-by:
Brice Dobry <brice.dobry@futurewei.com> Reviewed-by:
Ji Qiu <qiuji@iscas.ac.cn> Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn> Cr-Commit-Position: refs/heads/master@{#76128}
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- 24 Jun, 2021 1 commit
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Zheng Liu authored
Check whether the right most 16 bits are all-zero. Change-Id: I13bb8856888cbabc19c1f9354048f05ff9e4aacb Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2983839Reviewed-by:
Ji Qiu <qiuji@iscas.ac.cn> Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn> Cr-Commit-Position: refs/heads/master@{#75343}
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- 17 Jun, 2021 1 commit
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Lu Yahan authored
Change-Id: I0a614fa6c381770f56037f0401db008a37c71dca Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2966209 Auto-Submit: Yahan Lu <yahan@iscas.ac.cn> Commit-Queue: Ji Qiu <qiuji@iscas.ac.cn> Reviewed-by:
Ji Qiu <qiuji@iscas.ac.cn> Cr-Commit-Position: refs/heads/master@{#75199}
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- 10 Jun, 2021 1 commit
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Lu Yahan authored
In trampoline, we emit auipc+jalr first. But the offset between target and trampoline is less than int21, so we can use jal to replace auipc+jalr. It can reduce number of execution instruction. Change-Id: Idc37d80341030130c478209681cb54c63d1ddf27 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2939442 Auto-Submit: Yahan Lu <yahan@iscas.ac.cn> Commit-Queue: Brice Dobry <brice.dobry@futurewei.com> Reviewed-by:
Brice Dobry <brice.dobry@futurewei.com> Cr-Commit-Position: refs/heads/master@{#75072}
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- 28 May, 2021 1 commit
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Lu Yahan authored
And add s10 to scratch_register_list. Clean up t* register used in macroassembler Bug: v8:7703 Change-Id: Ib8477cd7528b8c2a2297da3f46659f30af45286e Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2914246Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Reviewed-by:
Brice Dobry <brice.dobry@futurewei.com> Commit-Queue: Yahan Lu <yahan@iscas.ac.cn> Cr-Commit-Position: refs/heads/master@{#74841}
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- 27 May, 2021 1 commit
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Derek Tu authored
Adds the following CB type RISC-V instructions to the assembler: c.beqz, c.bnez, c.andi, c.srai, c.srli. Also removes sext_xlen from RVC instructions c.xor, c.or, c.and. Change-Id: I96ce4693019c28235ccd4f85d0a68ca89a3f4096 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2912922Reviewed-by:
Brice Dobry <brice.dobry@futurewei.com> Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Commit-Queue: Brice Dobry <brice.dobry@futurewei.com> Cr-Commit-Position: refs/heads/master@{#74801}
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- 13 May, 2021 1 commit
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QiuJi authored
Bug: Change-Id: If5cb112f838e73bcec5e9971a12e1f88ab41e996 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2874399Reviewed-by:
Brice Dobry <brice.dobry@futurewei.com> Commit-Queue: Brice Dobry <brice.dobry@futurewei.com> Cr-Commit-Position: refs/heads/master@{#74549}
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- 12 May, 2021 1 commit
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QiuJi authored
Also handling kArchStackPointerGreaterThan in AssembleArchBoolean Change-Id: I253c1a6cb924364eead3b9fe58c7cf7d6f0696af Bug: v8:11737 Bug: v8:11747 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2876854Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Reviewed-by:
Brice Dobry <brice.dobry@futurewei.com> Commit-Queue: Brice Dobry <brice.dobry@futurewei.com> Cr-Commit-Position: refs/heads/master@{#74543}
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- 13 Apr, 2021 1 commit
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Yahan Lu authored
Clean todo comment in constant-riscv64.h about PCRelativeJumpRange. Change-Id: I9067134e96e4801fbd1f976d0e5d033085d5f133 Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2817975Reviewed-by:
Brice Dobry <brice.dobry@futurewei.com> Commit-Queue: Yahan Lu <yahan@iscas.ac.cn> Cr-Commit-Position: refs/heads/master@{#73925}
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- 12 Apr, 2021 1 commit
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Yahan Lu authored
Port pc-relative builtin-to-builtin calls. Port: ccc068d5 Change-Id: I1d11dd1e77ca578f7714864e4e090493fa8bca0a Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2814722 Commit-Queue: Yahan Lu <yahan@iscas.ac.cn> Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Reviewed-by:
Brice Dobry <brice.dobry@futurewei.com> Cr-Commit-Position: refs/heads/master@{#73894}
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- 09 Feb, 2021 1 commit
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Brice Dobry authored
This very large changeset adds support for RISC-V. Bug: v8:10991 Change-Id: Ic997c94cc12bba6881bc208e66526f423dd0679c Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2571344 Commit-Queue: Brice Dobry <brice.dobry@futurewei.com> Commit-Queue: Georg Neis <neis@chromium.org> Reviewed-by:
Georg Neis <neis@chromium.org> Reviewed-by:
Hannes Payer <hpayer@chromium.org> Reviewed-by:
Michael Achenbach <machenbach@chromium.org> Reviewed-by:
Michael Stanton <mvstanton@chromium.org> Cr-Commit-Position: refs/heads/master@{#72598}
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