- 20 Aug, 2018 1 commit
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Deepti Gandluri authored
Bug: v8:6532 Change-Id: Id89f81b12205900fc935e6232840e1976e24d3b4 Reviewed-on: https://chromium-review.googlesource.com/1176962 Commit-Queue: Deepti Gandluri <gdeepti@chromium.org> Reviewed-by:
Bill Budge <bbudge@chromium.org> Cr-Commit-Position: refs/heads/master@{#55228}
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- 14 Aug, 2018 2 commits
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Benedikt Meurer authored
This adds support for unaligned load/store access to the DataView backing store and uses byteswap operations to fix up the endianess when necessary. This changes the Word32ReverseBytes operator to be a required operator and adds the missing support on the Intel and ARM platforms (on 64-bit platforms the Word64ReverseBytes operator is also mandatory now). This further improves the performance on the dataviewperf.js test mentioned in the tracking bug by up to 40%, and at the same time reduces the code complexity in the EffectControlLinearizer. Bug: chromium:225811 Change-Id: I7c1ec826faf46a144a5a9068f8f815a5fd040997 Reviewed-on: https://chromium-review.googlesource.com/1174252Reviewed-by:
Sigurd Schneider <sigurds@chromium.org> Commit-Queue: Benedikt Meurer <bmeurer@chromium.org> Cr-Commit-Position: refs/heads/master@{#55111}
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Leszek Swirski authored
This reverts commit c46915b9. Reason for revert: Disasm failures https://ci.chromium.org/p/v8/builders/luci.v8.ci/V8%20Linux%20-%20debug/21727 Original change's description: > [turbofan] Further optimize DataView accesses. > > This adds support for unaligned load/store access to the DataView > backing store and uses byteswap operations to fix up the endianess > when necessary. This changes the Word32ReverseBytes operator to be > a required operator and adds the missing support on the Intel and > ARM platforms (on 64-bit platforms the Word64ReverseBytes operator > is also mandatory now). > > This further improves the performance on the dataviewperf.js test > mentioned in the tracking bug by up to 40%, and at the same time > reduces the code complexity in the EffectControlLinearizer. > > Bug: chromium:225811 > Change-Id: I296170b828c2ccc1c317ed37840b564aa14cdec2 > Reviewed-on: https://chromium-review.googlesource.com/1172777 > Commit-Queue: Benedikt Meurer <bmeurer@chromium.org> > Reviewed-by: Sigurd Schneider <sigurds@chromium.org> > Cr-Commit-Position: refs/heads/master@{#55099} TBR=sigurds@chromium.org,bmeurer@chromium.org Change-Id: If7a62e3a1a4ad26823fcbd2ab6eb4c053ad11c49 No-Presubmit: true No-Tree-Checks: true No-Try: true Bug: chromium:225811 Reviewed-on: https://chromium-review.googlesource.com/1174171Reviewed-by:
Leszek Swirski <leszeks@chromium.org> Commit-Queue: Leszek Swirski <leszeks@chromium.org> Cr-Commit-Position: refs/heads/master@{#55107}
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- 13 Aug, 2018 1 commit
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Benedikt Meurer authored
This adds support for unaligned load/store access to the DataView backing store and uses byteswap operations to fix up the endianess when necessary. This changes the Word32ReverseBytes operator to be a required operator and adds the missing support on the Intel and ARM platforms (on 64-bit platforms the Word64ReverseBytes operator is also mandatory now). This further improves the performance on the dataviewperf.js test mentioned in the tracking bug by up to 40%, and at the same time reduces the code complexity in the EffectControlLinearizer. Bug: chromium:225811 Change-Id: I296170b828c2ccc1c317ed37840b564aa14cdec2 Reviewed-on: https://chromium-review.googlesource.com/1172777 Commit-Queue: Benedikt Meurer <bmeurer@chromium.org> Reviewed-by:
Sigurd Schneider <sigurds@chromium.org> Cr-Commit-Position: refs/heads/master@{#55099}
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- 07 Aug, 2018 1 commit
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Sigurd Schneider authored
The instruction size in bytes is now kInstrSize on all platforms. Bug: v8:6666 Change-Id: I2f9880a6a74199a439c8327a4117efb74240aa22 Reviewed-on: https://chromium-review.googlesource.com/1164955 Commit-Queue: Sigurd Schneider <sigurds@chromium.org> Reviewed-by:
Michael Starzinger <mstarzinger@chromium.org> Reviewed-by:
Georg Neis <neis@chromium.org> Cr-Commit-Position: refs/heads/master@{#54944}
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- 03 Aug, 2018 1 commit
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Sigurd Schneider authored
We have two constants for the PC load delta; this CL consolidates them into one. The CL does not change MIPS as the two constants are defined to different values there. Bug: v8:6666 Change-Id: If207a59dea3ef33756a5d7330217ab8a176bdf63 Reviewed-on: https://chromium-review.googlesource.com/1161926Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Commit-Queue: Sigurd Schneider <sigurds@chromium.org> Cr-Commit-Position: refs/heads/master@{#54898}
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- 26 Jul, 2018 1 commit
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Clemens Hammacher authored
This ensures that tests actually abort on unimplemented opcodes instead of just printing them as "Unimplemented Instruction". If used to disassemble a code region though, we want to ignore unimplemented opcodes to keep printing remaining valid instructions. The tests were previously fixed by Deepti in 8fa509d3, but this got partly reverted on the "Address" refactoring in 2459046c. R=titzer@chromium.org Change-Id: I802dda2b0f45ee77c4f9b244ed984b1c4679bac3 Reviewed-on: https://chromium-review.googlesource.com/1146649 Commit-Queue: Clemens Hammacher <clemensh@chromium.org> Reviewed-by:
Ben Titzer <titzer@chromium.org> Cr-Commit-Position: refs/heads/master@{#54726}
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- 14 Apr, 2018 1 commit
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Jakob Kummerow authored
The "Address" type is V8's general-purpose type for manipulating memory addresses. Per the C++ spec, pointer arithmetic and pointer comparisons are undefined behavior except within the same array; since we generally don't operate within a C++ array, our general-purpose type shouldn't be a pointer type. Bug: v8:3770 Cq-Include-Trybots: luci.chromium.try:linux_chromium_rel_ng;master.tryserver.blink:linux_trusty_blink_rel Change-Id: Ib96016c24a0f18bcdba916dabd83e3f24a1b5779 Reviewed-on: https://chromium-review.googlesource.com/988657 Commit-Queue: Jakob Kummerow <jkummerow@chromium.org> Reviewed-by:
Leszek Swirski <leszeks@chromium.org> Cr-Commit-Position: refs/heads/master@{#52601}
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- 21 Feb, 2018 1 commit
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Martyn Capewell authored
Add support for CSDB in the 32-bit assembler, disassembler and simulator. Change-Id: I0e5432e4d219dd4699d5f9b7f911791acc87114c Reviewed-on: https://chromium-review.googlesource.com/928522Reviewed-by:
Ross McIlroy <rmcilroy@chromium.org> Commit-Queue: Martyn Capewell <martyn.capewell@arm.com> Cr-Commit-Position: refs/heads/master@{#51425}
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- 10 Jan, 2018 1 commit
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Pierre Langlois authored
Disallow using the PC as a base in LDR and instead provide a dedicated assembler method for pc-relative loads. The reason for this is that the generic `Assembler::ldr` method may decide to generate more instructions if the offset is out of range, and if the PC was the base, we would get surprising results. For example: ~~~ ldr r0, [pc, #0xcabba9e] ~~~ is not equivalent to: ~~~ movw ip, #0xba9e movt ip, #0xcab ldr r0, [pc, ip] ~~~ since the reference to the PC has moved down two instructions! We could teach the assembler to handle those cases correctly, but pc-relative loads are used in specific cases only so that's not necessary. As a drive-by, remove a reference to code aging. Bug: Change-Id: I586d83a418db52cf28d3b524f889bf40f077998a Reviewed-on: https://chromium-review.googlesource.com/847008Reviewed-by:
Jaroslav Sevcik <jarin@chromium.org> Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Cr-Commit-Position: refs/heads/master@{#50475}
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- 02 Dec, 2017 1 commit
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Mathias Bynens authored
This patch normalizes the casing of hexadecimal digits in escape sequences of the form `\xNN` and integer literals of the form `0xNNNN`. Previously, the V8 code base used an inconsistent mixture of uppercase and lowercase. Google’s C++ style guide uses uppercase in its examples: https://google.github.io/styleguide/cppguide.html#Non-ASCII_Characters Moreover, uppercase letters more clearly stand out from the lowercase `x` (or `u`) characters at the start, as well as lowercase letters elsewhere in strings. BUG=v8:7109 TBR=marja@chromium.org,titzer@chromium.org,mtrofin@chromium.org,mstarzinger@chromium.org,rossberg@chromium.org,yangguo@chromium.org,mlippautz@chromium.org NOPRESUBMIT=true Cq-Include-Trybots: master.tryserver.blink:linux_trusty_blink_rel;master.tryserver.chromium.linux:linux_chromium_rel_ng Change-Id: I790e21c25d96ad5d95c8229724eb45d2aa9e22d6 Reviewed-on: https://chromium-review.googlesource.com/804294 Commit-Queue: Mathias Bynens <mathias@chromium.org> Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Cr-Commit-Position: refs/heads/master@{#49810}
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- 18 Oct, 2017 1 commit
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Clemens Hammacher authored
This CL fixes all occurences that don't require special OWNER reviews, or can be reviewed by Michi. After this one, we should be able to reenable the readability/check cpplint check. R=mstarzinger@chromium.org Bug: v8:6837, v8:6921 Cq-Include-Trybots: master.tryserver.chromium.linux:linux_chromium_rel_ng;master.tryserver.v8:v8_linux_noi18n_rel_ng Change-Id: Ic81d68d5534eaa795b7197fed5c41ed158361d62 Reviewed-on: https://chromium-review.googlesource.com/721120 Commit-Queue: Clemens Hammacher <clemensh@chromium.org> Reviewed-by:
Michael Starzinger <mstarzinger@chromium.org> Cr-Commit-Position: refs/heads/master@{#48670}
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- 17 Oct, 2017 1 commit
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Clemens Hammacher authored
This prepares fixes in the implementations of vabs and vneg (potentially more). In order to implement them correctly, we need to preserve the exact bit pattern. R=ahaas@chromium.org, rodolph.perfetta@arm.com Bug: v8:6947 Change-Id: I7194a60371a6e3c9ffba32981c90090ffafaa610 Reviewed-on: https://chromium-review.googlesource.com/722941Reviewed-by:
Rodolph Perfetta <rodolph.perfetta@arm.com> Reviewed-by:
Andreas Haas <ahaas@chromium.org> Commit-Queue: Clemens Hammacher <clemensh@chromium.org> Cr-Commit-Position: refs/heads/master@{#48648}
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- 03 Aug, 2017 1 commit
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Michael Starzinger authored
This removes the obsolete {Crankshaft} factory method as it returns the same configuration as the {Turbofan} factory by now. We now consistently use {RegisterConfiguration::Default} everywhere. R=jkummerow@chromium.org BUG=v8:6408 Change-Id: I6be25774aa6714ef4dc1ef6856bb6dbc95593a29 Reviewed-on: https://chromium-review.googlesource.com/597858Reviewed-by:
Jakob Kummerow <jkummerow@chromium.org> Commit-Queue: Michael Starzinger <mstarzinger@chromium.org> Cr-Commit-Position: refs/heads/master@{#47109}
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- 02 Aug, 2017 1 commit
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Julien Brianceau authored
Bug: chromium:750830 Cq-Include-Trybots: master.tryserver.blink:linux_trusty_blink_rel;master.tryserver.chromium.linux:linux_chromium_rel_ng;master.tryserver.v8:v8_linux_noi18n_rel_ng Change-Id: Icab7b5a1c469d5e77d04df8bfca8319784e92af4 Reviewed-on: https://chromium-review.googlesource.com/595655 Commit-Queue: Julien Brianceau <jbriance@cisco.com> Reviewed-by:
Yang Guo <yangguo@chromium.org> Reviewed-by:
Michael Starzinger <mstarzinger@chromium.org> Reviewed-by:
Clemens Hammacher <clemensh@chromium.org> Reviewed-by:
Daniel Ehrenberg <littledan@chromium.org> Cr-Commit-Position: refs/heads/master@{#47072}
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- 13 Jul, 2017 1 commit
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Pierre Langlois authored
When disassembling some instructions we would print `r12`, which can be confusing when the rest of the disassembly consistently uses `ip`. Bug: Change-Id: Id4cfc5805ef102a0845cdaaa8390e618ee981b19 Reviewed-on: https://chromium-review.googlesource.com/570038Reviewed-by:
Georg Neis <neis@chromium.org> Commit-Queue: Pierre Langlois <pierre.langlois@arm.com> Cr-Commit-Position: refs/heads/master@{#46628}
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- 22 May, 2017 2 commits
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Wiktor Garbacz authored
Change-Id: I20ed35a7fb5104a9cc66bb54fa8966589c43d7f9 Reviewed-on: https://chromium-review.googlesource.com/507287Reviewed-by:
Andreas Haas <ahaas@chromium.org> Reviewed-by:
Benedikt Meurer <bmeurer@chromium.org> Reviewed-by:
Daniel Clifford <danno@chromium.org> Reviewed-by:
Jakob Gruber <jgruber@chromium.org> Reviewed-by:
Marja Hölttä <marja@chromium.org> Reviewed-by:
Jochen Eisinger <jochen@chromium.org> Commit-Queue: Wiktor Garbacz <wiktorg@google.com> Cr-Commit-Position: refs/heads/master@{#45458}
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honggyu.kp authored
This patch fixes the below compilation error with a static_cast. ../src/arm/disasm-arm.cc:689:72: error: format specifies type 'void *' but the argument has type 'v8::internal::byte *' (aka 'unsigned char *') [-Werror,-Wformat-pedantic] out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%p", addr); R=yangguo@chromium.org Review-Url: https://codereview.chromium.org/2900663002 Cr-Commit-Position: refs/heads/master@{#45457}
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- 16 May, 2017 1 commit
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bbudge authored
- Adds vdup.<size> Dd/Qd, Dm[i] instruction. - Adds vsli, vsri instructions. - Changes VMovExtended to use these to avoid moves to core registers. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2868603002 Cr-Commit-Position: refs/heads/master@{#45351}
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- 15 May, 2017 1 commit
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georgia.kouveli authored
BUG= Review-Url: https://codereview.chromium.org/2871863003 Cr-Commit-Position: refs/heads/master@{#45297}
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- 24 Apr, 2017 1 commit
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bbudge authored
- Adds new F32x4AddHoriz, I32x4AddHoriz, etc. to WASM opcodes. - Implements them for ARM. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2804883008 Cr-Commit-Position: refs/heads/master@{#44812}
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- 10 Apr, 2017 3 commits
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bbudge authored
LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2797923006 Cr-Original-Commit-Position: refs/heads/master@{#44536} Committed: https://chromium.googlesource.com/v8/v8/+/6588187ae3acaa5b40762c539ee9fe355551bea3 Review-Url: https://codereview.chromium.org/2797923006 Cr-Commit-Position: refs/heads/master@{#44540}
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bbudge authored
Revert of [ARM] Implement D-register versions of vzip, vuzp, and vtrn. (patchset #4 id:60001 of https://codereview.chromium.org/2797923006/ ) Reason for revert: Breaks: http://builders/V8%20Arm%20-%20debug/builds/2751 Original issue's description: > [ARM] Implement D-register versions of vzip, vuzp, and vtrn. > > LOG=N > BUG=v8:6020 > > Review-Url: https://codereview.chromium.org/2797923006 > Cr-Commit-Position: refs/heads/master@{#44536} > Committed: https://chromium.googlesource.com/v8/v8/+/6588187ae3acaa5b40762c539ee9fe355551bea3 TBR=martyn.capewell@arm.com,bmeurer@chromium.org # Skipping CQ checks because original CL landed less than 1 days ago. NOPRESUBMIT=true NOTREECHECKS=true NOTRY=true BUG=v8:6020 Review-Url: https://codereview.chromium.org/2810703003 Cr-Commit-Position: refs/heads/master@{#44537}
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bbudge authored
LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2797923006 Cr-Commit-Position: refs/heads/master@{#44536}
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- 27 Mar, 2017 1 commit
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bbudge authored
- Fixes vmovl for widening 16 to 32, 32 to 64. - Adds vqmovn. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2773303002 Cr-Commit-Position: refs/heads/master@{#44156}
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- 14 Mar, 2017 1 commit
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bbudge authored
- Implements vuzp, vtrn instructions for q-registers. - Refactors vmvn, vswp to use common unary op helper fn. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2739033002 Cr-Commit-Position: refs/heads/master@{#43795}
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- 09 Mar, 2017 1 commit
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yangguo authored
We used to embed a string address as description right after a stop instruction, which the simulator would read and print. We removed that a while ago to make the snapshot predictable. R=petermarshall@chromium.org BUG=v8:6071 Review-Url: https://codereview.chromium.org/2744503003 Cr-Commit-Position: refs/heads/master@{#43698}
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- 02 Mar, 2017 1 commit
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bbudge authored
- Implements Select instructions using a single ARM vbsl instruction. - Renames boolean machine operators to match renamed S1xN machine types. - Implements S1xN vector logical ops, AND, OR, XOR, NOT for ARM. - Implements S1xN AnyTrue, AllTrue ops for ARM. - Eliminates unused SIMD op categories in opcodes.h. LOG=N BUG=v8:6020 Review-Url: https://codereview.chromium.org/2711863002 Cr-Commit-Position: refs/heads/master@{#43556}
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- 01 Feb, 2017 1 commit
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bbudge authored
- Adds vqadd.s/u, vqsub.s/u for all integer lane sizes. - Refactors disassembler and simulator, using switches instead of long if-else chains. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2649323012 Cr-Commit-Position: refs/heads/master@{#42865}
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- 23 Jan, 2017 1 commit
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bbudge authored
LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2629223005 Cr-Commit-Position: refs/heads/master@{#42610}
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- 16 Jan, 2017 1 commit
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bbudge authored
- Adds vmin, vmax for FP and integer vectors, both signed and unsigned. - Regularizes switching logic in disasm and simulator for special codes 4 and 6. - Factors vrecpe, vrsqrte, vrecps, vrsqrts into helper fns. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2623993006 Cr-Commit-Position: refs/heads/master@{#42385}
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- 12 Jan, 2017 2 commits
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bbudge authored
LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2620343002 Cr-Commit-Position: refs/heads/master@{#42273}
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bbudge authored
- Floating point, signed, and unsigned. - Disassembler, simulator support too. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2602293002 Cr-Commit-Position: refs/heads/master@{#42262}
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- 10 Jan, 2017 1 commit
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bbudge authored
- Disassembler, simulator support too. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2600153002 Cr-Commit-Position: refs/heads/master@{#42176}
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- 06 Jan, 2017 1 commit
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martyn.capewell authored
Remove unused size variable from disassembler. BUG= Review-Url: https://codereview.chromium.org/2615633004 Cr-Commit-Position: refs/heads/master@{#42107}
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- 20 Dec, 2016 1 commit
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bbudge authored
LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2593443002 Cr-Commit-Position: refs/heads/master@{#41859}
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- 17 Dec, 2016 1 commit
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bbudge authored
- Adds vabs, vneg, vmul, vext, vzip, vrev instructions. - Adds Swizzle function to macro assembler. - Simplifies if-else logic in disassembler, simulator, for Neon special. - Some refactoring of Neon assembler, macro-assembler tests. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2579913002 Cr-Commit-Position: refs/heads/master@{#41781}
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- 15 Dec, 2016 1 commit
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bbudge authored
- Adds NEON instructions to assembler, disassembler, simulator. - Adds ExtractLane, ReplaceLane functions to macro assembler. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2546933002 Cr-Commit-Position: refs/heads/master@{#41737}
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- 25 Nov, 2016 1 commit
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bbudge authored
- Adds vmov, vswp instructions for QwNeonRegisters. - Refactors existing vswp implementation, moves non-Neon adaption to MacroAssembler. - Adds simd128 support to CodeGenerator AssembleMove, AssembleSwap. LOG=N BUG=v8:4124 Review-Url: https://codereview.chromium.org/2523933002 Cr-Commit-Position: refs/heads/master@{#41291}
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- 08 Sep, 2016 1 commit
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martyn.capewell authored
Reason for revert: Breaks g++ build. Original issue's description: > [turbofan] ARM: Implement vswp and use in gap resolver > > Use vswp to switch double-precision registers in the gap resolver, with fall > back temp register-based code if NEON is not available. > > BUG= > > Committed: https://crrev.com/2837c2e65a2ee5b9fc610f30ce1215f52323ecbd > Cr-Commit-Position: refs/heads/master@{#39209} BUG= Review-Url: https://codereview.chromium.org/2314043002 Cr-Commit-Position: refs/heads/master@{#39264}
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