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  1. 13 Jan, 2021 5 commits
  3. 12 Jan, 2021 32 commits
  5. 11 Jan, 2021 3 commits
    • Milad Fa's avatar
      PPC: [wasm-simd] Prototype extended pairwise addition · c5fc192e
      Milad Fa authored 
      Bug: v8:11086
Change-Id: Ib896020b0865c0f87cabbde254bc8af36ce705d3
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2623007Reviewed-by: 's avatarJunliang Yan <junyan@redhat.com>
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/master@{#72020}
      c5fc192e
    • Andrew Comminos's avatar
      [cpu-profiler] Optimize CodeMap implementation · fbdcef31
      Andrew Comminos authored 
      Currently, the CodeMap utilizes double indirection into a deque for
entries in its map. Since we don't reuse CodeEntry objects, this doesn't
confer any benefits really -- avoid this step and save memory by
maintaining only a single mapping.

Bug: v8:11054
Change-Id: I2cbc188ff64dd2faa9c4c03d9892b4c8e5e68794
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2617746Reviewed-by: 's avatarPeter Marshall <petermarshall@chromium.org>
Commit-Queue: Andrew Comminos <acomminos@fb.com>
Cr-Commit-Position: refs/heads/master@{#72019}
      fbdcef31
    • Andreas Haas's avatar
      [wasm][liftoff] Delay use counter decrement of PeekToRegister · 48ead1a8
      Andreas Haas authored 
      This CL fixes a bug in the code generation for I32AtomicCompareExchange
in Liftoff on ia32. The problem is the inconsistency that
LiftoffAssembler::PeekToRegister(...) introduces to the cache state.
PeekToRegister loads the value from the value stack into a register, but
does not pop the value off the stack. When the value was already stored
in a register, the use counter of that register gets decreased, even
though the value is still on the stack.

The problem arises when this register later gets reused, which is
necessary unfortunately on ia32. When SpillRegister is called for this
register, all stack values that are stored in this register get written
to memory. SpillRegister uses the use counter of the register to detect
when the register was spilled to all stack slots that were cached by
this register. However, as described above, the value stack and the use
counter are inconsistent at that moment, so SpillRegister finishes
early and does not spill the register to all stack values, and this
causes the bug later.

With this CL the decrement of the use counter gets delayed until when
the value actually gets popped off the stack.

R=clemensb@chromium.org

Bug: chromium:1145135
Change-Id: I07cb256a7e5135dbce41b246c120650635ad2758
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2602464Reviewed-by: 's avatarClemens Backes <clemensb@chromium.org>
Commit-Queue: Andreas Haas <ahaas@chromium.org>
Cr-Commit-Position: refs/heads/master@{#72018}
      48ead1a8