ARM: Special code for raising to the power of an integer

When calculating Math.pow where the exponent is a smi use a simple loop to calculate the result.

Added support for the vmov instruction moving from one doubleword extension register to another.

Added some Math.pow tests which partially covers what is in the Sputnik tests.
Review URL: http://codereview.chromium.org/2804033

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@4990 ce2b1a6d-e550-0410-aec6-3dcde31c8c00

src/arm/assembler-arm.cc

@@ -1801,6 +1801,16 @@ void Assembler::vstr(const DwVfpRegister src,
 }
 
 
+void Assembler::vmov(const DwVfpRegister dst,
+                     const DwVfpRegister src,
+                     const Condition cond) {
+  // Dd = Dm
+  // Instruction details available in ARM DDI 0406B, A8-642.
+  emit(cond | 0xE*B24 | 0xB*B20 |
+       dst.code()*B12 | 0x5*B9 | B8 | B6 | src.code());
+}
+
+
 void Assembler::vmov(const DwVfpRegister dst,
                      const Register src1,
                      const Register src2,

src/arm/assembler-arm.h

@@ -930,6 +930,10 @@ class Assembler : public Malloced {
             const Register base,
             int offset,  // Offset must be a multiple of 4.
             const Condition cond = al);
+
+  void vmov(const DwVfpRegister dst,
+            const DwVfpRegister src,
+            const Condition cond = al);
   void vmov(const DwVfpRegister dst,
             const Register src1,
             const Register src2,

src/arm/codegen-arm.cc

@@ -4291,7 +4291,7 @@ void CodeGenerator::GenerateMathPow(ZoneList<Expression*>* args) {
   } else {
     CpuFeatures::Scope scope(VFP3);
     JumpTarget runtime, done;
-    Label not_minus_half, allocate_return;
+    Label exponent_nonsmi, base_nonsmi, powi, not_minus_half, allocate_return;
 
     Register scratch1 = VirtualFrame::scratch0();
     Register scratch2 = VirtualFrame::scratch1();
@@ -4299,18 +4299,64 @@ void CodeGenerator::GenerateMathPow(ZoneList<Expression*>* args) {
     // Get base and exponent to registers.
     Register exponent = frame_->PopToRegister();
     Register base = frame_->PopToRegister(exponent);
+    Register heap_number_map = no_reg;
 
     // Set the frame for the runtime jump target. The code below jumps to the
     // jump target label so the frame needs to be established before that.
     ASSERT(runtime.entry_frame() == NULL);
     runtime.set_entry_frame(frame_);
 
-    __ BranchOnSmi(exponent, runtime.entry_label());
+    __ BranchOnNotSmi(exponent, &exponent_nonsmi);
+    __ BranchOnNotSmi(base, &base_nonsmi);
 
+    heap_number_map = r6;
+    __ LoadRoot(heap_number_map, Heap::kHeapNumberMapRootIndex);
+
+    // Exponent is a smi and base is a smi. Get the smi value into vfp register
+    // d1.
+    __ SmiToDoubleVFPRegister(base, d1, scratch1, s0);
+    __ b(&powi);
+
+    __ bind(&base_nonsmi);
+    // Exponent is smi and base is non smi. Get the double value from the base
+    // into vfp register d1.
+    __ ObjectToDoubleVFPRegister(base, d1,
+                                 scratch1, scratch2, heap_number_map, s0,
+                                 runtime.entry_label());
+
+    __ bind(&powi);
+
+    // Load 1.0 into d0.
+    __ mov(scratch2, Operand(0x3ff00000));
+    __ mov(scratch1, Operand(0));
+    __ vmov(d0, scratch1, scratch2);
+
+    // Get the absolute untagged value of the exponent and use that for the
+    // calculation.
+    __ mov(scratch1, Operand(exponent, ASR, kSmiTagSize), SetCC);
+    __ rsb(scratch1, scratch1, Operand(0), LeaveCC, mi);  // Negate if negative.
+    __ vmov(d2, d0, mi);  // 1.0 needed in d2 later if exponent is negative.
+
+    // Run through all the bits in the exponent. The result is calculated in d0
+    // and d1 holds base^(bit^2).
+    Label more_bits;
+    __ bind(&more_bits);
+    __ mov(scratch1, Operand(scratch1, LSR, 1), SetCC);
+    __ vmul(d0, d0, d1, cs);  // Multiply with base^(bit^2) if bit is set.
+    __ vmul(d1, d1, d1, ne);  // Don't bother calculating next d1 if done.
+    __ b(ne, &more_bits);
+
+    // If exponent is negative result is 1/result (d2 already holds 1.0 in that
+    // case).
+    __ cmp(exponent, Operand(0));
+    __ vdiv(d0, d2, d0, mi);
+    __ b(&allocate_return);
+
+    __ bind(&exponent_nonsmi);
     // Special handling of raising to the power of -0.5 and 0.5. First check
     // that the value is a heap number and that the lower bits (which for both
     // values are zero).
-    Register heap_number_map = r6;
+    heap_number_map = r6;
     __ LoadRoot(heap_number_map, Heap::kHeapNumberMapRootIndex);
     __ ldr(scratch1, FieldMemOperand(exponent, HeapObject::kMapOffset));
     __ ldr(scratch2, FieldMemOperand(exponent, HeapNumber::kMantissaOffset));
@@ -4319,7 +4365,7 @@ void CodeGenerator::GenerateMathPow(ZoneList<Expression*>* args) {
     __ tst(scratch2, scratch2);
     runtime.Branch(ne);
 
-    // Load the e
+    // Load the higher bits (which contains the floating point exponent).
     __ ldr(scratch1, FieldMemOperand(exponent, HeapNumber::kExponentOffset));
 
     // Compare exponent with -0.5.

src/arm/disasm-arm.cc

@@ -1047,7 +1047,14 @@ void Decoder::DecodeTypeVFP(Instr* instr) {
   if (instr->Bit(4) == 0) {
     if (instr->Opc1Field() == 0x7) {
       // Other data processing instructions
-      if ((instr->Opc2Field() == 0x7) && (instr->Opc3Field() == 0x3)) {
+      if ((instr->Opc2Field() == 0x0) && (instr->Opc3Field() == 0x1)) {
+        // vmov register to register.
+        if (instr->SzField() == 0x1) {
+          Format(instr, "vmov.f64'cond 'Dd, 'Dm");
+        } else {
+          Unknown(instr);  // Not used by V8.
+        }
+      } else if ((instr->Opc2Field() == 0x7) && (instr->Opc3Field() == 0x3)) {
         DecodeVCVTBetweenDoubleAndSingle(instr);
       } else if ((instr->Opc2Field() == 0x8) && (instr->Opc3Field() & 0x1)) {
         DecodeVCVTBetweenFloatingPointAndInteger(instr);

src/arm/simulator-arm.cc

@@ -2276,7 +2276,14 @@ void Simulator::DecodeTypeVFP(Instr* instr) {
   if (instr->Bit(4) == 0) {
     if (instr->Opc1Field() == 0x7) {
       // Other data processing instructions
-      if ((instr->Opc2Field() == 0x7) && (instr->Opc3Field() == 0x3)) {
+      if ((instr->Opc2Field() == 0x0) && (instr->Opc3Field() == 0x1)) {
+        // vmov register to register.
+        if (instr->SzField() == 0x1) {
+          set_d_register_from_double(vd, get_double_from_d_register(vm));
+        } else {
+          UNREACHABLE();  // Not used by V8.
+        }
+      } else if ((instr->Opc2Field() == 0x7) && (instr->Opc3Field() == 0x3)) {
         DecodeVCVTBetweenDoubleAndSingle(instr);
       } else if ((instr->Opc2Field() == 0x8) && (instr->Opc3Field() & 0x1)) {
         DecodeVCVTBetweenFloatingPointAndInteger(instr);

test/cctest/test-disasm-arm.cc

@@ -408,6 +408,11 @@ TEST(Vfp) {
 
   if (CpuFeatures::IsSupported(VFP3)) {
     CpuFeatures::Scope scope(VFP3);
+    COMPARE(vmov(d0, d1),
+            "eeb00b41       vmov.f64 d0, d1");
+    COMPARE(vmov(d3, d3, eq),
+            "0eb03b43       vmov.f64eq d3, d3");
+
     COMPARE(vadd(d0, d1, d2),
             "ee310b02       vadd.f64 d0, d1, d2");
     COMPARE(vadd(d3, d4, d5, mi),

test/mjsunit/math-pow.js

+// Copyright 2010 the V8 project authors. All rights reserved.
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+//
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     * Redistributions in binary form must reproduce the above
+//       copyright notice, this list of conditions and the following
+//       disclaimer in the documentation and/or other materials provided
+//       with the distribution.
+//     * Neither the name of Google Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+// Tests the special cases specified by ES 15.8.2.13
+
+// Simple sanity check
+assertEquals(4, Math.pow(2, 2));
+assertEquals(2147483648, Math.pow(2, 31));
+assertEquals(0.25, Math.pow(2, -2));
+assertEquals(0.0625, Math.pow(2, -4));
+assertEquals(1, Math.pow(1, 100));
+assertEquals(0, Math.pow(0, 1000));
+
+// Spec tests
+assertEquals(NaN, Math.pow(2, NaN));
+assertEquals(NaN, Math.pow(+0, NaN));
+assertEquals(NaN, Math.pow(-0, NaN));
+assertEquals(NaN, Math.pow(Infinity, NaN));
+assertEquals(NaN, Math.pow(-Infinity, NaN));
+
+assertEquals(1, Math.pow(NaN, +0));
+assertEquals(1, Math.pow(NaN, -0));
+
+assertEquals(NaN, Math.pow(NaN, NaN));
+assertEquals(NaN, Math.pow(NaN, 2.2));
+assertEquals(NaN, Math.pow(NaN, 1));
+assertEquals(NaN, Math.pow(NaN, -1));
+assertEquals(NaN, Math.pow(NaN, -2.2));
+assertEquals(NaN, Math.pow(NaN, Infinity));
+assertEquals(NaN, Math.pow(NaN, -Infinity));
+
+assertEquals(Infinity, Math.pow(1.1, Infinity));
+assertEquals(Infinity, Math.pow(-1.1, Infinity));
+assertEquals(Infinity, Math.pow(2, Infinity));
+assertEquals(Infinity, Math.pow(-2, Infinity));
+
+assertEquals(+0, Math.pow(1.1, -Infinity));
+assertEquals(+0, Math.pow(-1.1, -Infinity));
+assertEquals(+0, Math.pow(2, -Infinity));
+assertEquals(+0, Math.pow(-2, -Infinity));
+
+assertEquals(NaN, Math.pow(1, Infinity));
+assertEquals(NaN, Math.pow(1, -Infinity));
+assertEquals(NaN, Math.pow(-1, Infinity));
+assertEquals(NaN, Math.pow(-1, -Infinity));
+
+assertEquals(+0, Math.pow(0.1, Infinity));
+assertEquals(+0, Math.pow(-0.1, Infinity));
+assertEquals(+0, Math.pow(0.999, Infinity));
+assertEquals(+0, Math.pow(-0.999, Infinity));
+
+assertEquals(Infinity, Math.pow(0.1, -Infinity));
+assertEquals(Infinity, Math.pow(-0.1, -Infinity));
+assertEquals(Infinity, Math.pow(0.999, -Infinity));
+assertEquals(Infinity, Math.pow(-0.999, -Infinity));
+
+assertEquals(Infinity, Math.pow(Infinity, 0.1));
+assertEquals(Infinity, Math.pow(Infinity, 2));
+
+assertEquals(+0, Math.pow(Infinity, -0.1));
+assertEquals(+0, Math.pow(Infinity, -2));
+
+assertEquals(-Infinity, Math.pow(-Infinity, 3));
+assertEquals(-Infinity, Math.pow(-Infinity, 13));
+
+assertEquals(Infinity, Math.pow(-Infinity, 3.1));
+assertEquals(Infinity, Math.pow(-Infinity, 2));
+
+assertEquals(-0, Math.pow(-Infinity, -3));
+assertEquals(-0, Math.pow(-Infinity, -13));
+
+assertEquals(+0, Math.pow(-Infinity, -3.1));
+assertEquals(+0, Math.pow(-Infinity, -2));
+
+assertEquals(+0, Math.pow(+0, 1.1));
+assertEquals(+0, Math.pow(+0, 2));
+
+assertEquals(Infinity, Math.pow(+0, -1.1));
+assertEquals(Infinity, Math.pow(+0, -2));
+
+assertEquals(-0, Math.pow(-0, 3));
+assertEquals(-0, Math.pow(-0, 13));
+
+assertEquals(+0, Math.pow(-0, 3.1));
+assertEquals(+0, Math.pow(-0, 2));
+
+assertEquals(-Infinity, Math.pow(-0, -3));
+assertEquals(-Infinity, Math.pow(-0, -13));
+
+assertEquals(Infinity, Math.pow(-0, -3.1));
+assertEquals(Infinity, Math.pow(-0, -2));
+
+assertEquals(NaN, Math.pow(-0.00001, 1.1));
+assertEquals(NaN, Math.pow(-0.00001, -1.1));
+assertEquals(NaN, Math.pow(-1.1, 1.1));
+assertEquals(NaN, Math.pow(-1.1, -1.1));
+assertEquals(NaN, Math.pow(-2, 1.1));
+assertEquals(NaN, Math.pow(-2, -1.1));
+assertEquals(NaN, Math.pow(-1000, 1.1));
+assertEquals(NaN, Math.pow(-1000, -1.1));