PPC: [wasm-simd] Implement f32x4 and f64x2 pmin and pmax

Change-Id: I58301ded85db096ea5d141b36eb628d0cea54256
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2533353
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Reviewed-by: Junliang Yan <junyan@redhat.com>
Cr-Commit-Position: refs/heads/master@{#71154}

src/compiler/backend/ppc/code-generator-ppc.cc

@@ -3417,6 +3417,38 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
                   i.InputSimd128Register(1), kScratchDoubleReg);
       break;
     }
+    case kPPC_F32x4Pmin: {
+      Simd128Register dst = i.OutputSimd128Register(),
+                      src0 = i.InputSimd128Register(0),
+                      src1 = i.InputSimd128Register(1);
+      __ xvcmpgtsp(kScratchDoubleReg, src0, src1);
+      __ vsel(dst, src0, src1, kScratchDoubleReg);
+      break;
+    }
+    case kPPC_F32x4Pmax: {
+      Simd128Register dst = i.OutputSimd128Register(),
+                      src0 = i.InputSimd128Register(0),
+                      src1 = i.InputSimd128Register(1);
+      __ xvcmpgtsp(kScratchDoubleReg, src1, src0);
+      __ vsel(dst, src0, src1, kScratchDoubleReg);
+      break;
+    }
+    case kPPC_F64x2Pmin: {
+      Simd128Register dst = i.OutputSimd128Register(),
+                      src0 = i.InputSimd128Register(0),
+                      src1 = i.InputSimd128Register(1);
+      __ xvcmpgtdp(kScratchDoubleReg, src0, src1);
+      __ vsel(dst, src0, src1, kScratchDoubleReg);
+      break;
+    }
+    case kPPC_F64x2Pmax: {
+      Simd128Register dst = i.OutputSimd128Register(),
+                      src0 = i.InputSimd128Register(0),
+                      src1 = i.InputSimd128Register(1);
+      __ xvcmpgtdp(kScratchDoubleReg, src1, src0);
+      __ vsel(dst, src0, src1, kScratchDoubleReg);
+      break;
+    }
     case kPPC_StoreCompressTagged: {
       ASSEMBLE_STORE_INTEGER(StoreTaggedField, StoreTaggedFieldX);
       break;

src/compiler/backend/ppc/instruction-codes-ppc.h

@@ -214,6 +214,8 @@ namespace compiler {
   V(PPC_F64x2Floor)                  \
   V(PPC_F64x2Trunc)                  \
   V(PPC_F64x2NearestInt)             \
+  V(PPC_F64x2Pmin)                   \
+  V(PPC_F64x2Pmax)                   \
   V(PPC_F32x4Splat)                  \
   V(PPC_F32x4ExtractLane)            \
   V(PPC_F32x4ReplaceLane)            \
@@ -239,6 +241,8 @@ namespace compiler {
   V(PPC_F32x4Floor)                  \
   V(PPC_F32x4Trunc)                  \
   V(PPC_F32x4NearestInt)             \
+  V(PPC_F32x4Pmin)                   \
+  V(PPC_F32x4Pmax)                   \
   V(PPC_I64x2Splat)                  \
   V(PPC_I64x2ExtractLane)            \
   V(PPC_I64x2ReplaceLane)            \

src/compiler/backend/ppc/instruction-scheduler-ppc.cc

@@ -137,6 +137,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kPPC_F64x2Floor:
     case kPPC_F64x2Trunc:
     case kPPC_F64x2NearestInt:
+    case kPPC_F64x2Pmin:
+    case kPPC_F64x2Pmax:
     case kPPC_F32x4Splat:
     case kPPC_F32x4ExtractLane:
     case kPPC_F32x4ReplaceLane:
@@ -164,6 +166,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kPPC_F32x4Floor:
     case kPPC_F32x4Trunc:
     case kPPC_F32x4NearestInt:
+    case kPPC_F32x4Pmin:
+    case kPPC_F32x4Pmax:
     case kPPC_I64x2Splat:
     case kPPC_I64x2ExtractLane:
     case kPPC_I64x2ReplaceLane:

src/compiler/backend/ppc/instruction-selector-ppc.cc

@@ -2389,6 +2389,18 @@ SIMD_VISIT_BITMASK(I8x16BitMask)
 SIMD_VISIT_BITMASK(I16x8BitMask)
 SIMD_VISIT_BITMASK(I32x4BitMask)
 #undef SIMD_VISIT_BITMASK
+
+#define SIMD_VISIT_PMIN_MAX(Type)                                           \
+  void InstructionSelector::Visit##Type(Node* node) {                       \
+    PPCOperandGenerator g(this);                                            \
+    Emit(kPPC_##Type, g.DefineAsRegister(node),                             \
+         g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1))); \
+  }
+SIMD_VISIT_PMIN_MAX(F64x2Pmin)
+SIMD_VISIT_PMIN_MAX(F32x4Pmin)
+SIMD_VISIT_PMIN_MAX(F64x2Pmax)
+SIMD_VISIT_PMIN_MAX(F32x4Pmax)
+#undef SIMD_VISIT_PMIN_MAX
 #undef SIMD_TYPES
 
 void InstructionSelector::VisitI8x16Shuffle(Node* node) {
@@ -2457,14 +2469,6 @@ void InstructionSelector::EmitPrepareResults(
 
 void InstructionSelector::VisitLoadTransform(Node* node) { UNIMPLEMENTED(); }
 
-void InstructionSelector::VisitF32x4Pmin(Node* node) { UNIMPLEMENTED(); }
-
-void InstructionSelector::VisitF32x4Pmax(Node* node) { UNIMPLEMENTED(); }
-
-void InstructionSelector::VisitF64x2Pmin(Node* node) { UNIMPLEMENTED(); }
-
-void InstructionSelector::VisitF64x2Pmax(Node* node) { UNIMPLEMENTED(); }
-
 // static
 MachineOperatorBuilder::Flags
 InstructionSelector::SupportedMachineOperatorFlags() {