[wasm-simd][arm] Prototype i64x2.eq

Bug: v8:11215
Change-Id: I71b47fab37a92e1b988a613b234694a57e21a9d5
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2567533Reviewed-by: Bill Budge <bbudge@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#71604}

src/compiler/backend/arm/code-generator-arm.cc

@@ -2407,6 +2407,16 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
               i.InputSimd128Register(1));
       break;
     }
+    case kArmI64x2Eq: {
+      Simd128Register dst = i.OutputSimd128Register();
+      UseScratchRegisterScope temps(tasm());
+      Simd128Register scratch = temps.AcquireQ();
+      __ vceq(Neon32, dst, i.InputSimd128Register(0),
+              i.InputSimd128Register(1));
+      __ vrev64(Neon32, scratch, dst);
+      __ vand(dst, dst, scratch);
+      break;
+    }
     case kArmI32x4Eq: {
       __ vceq(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0),
               i.InputSimd128Register(1));

src/compiler/backend/arm/instruction-codes-arm.h

@@ -183,6 +183,7 @@ namespace compiler {
   V(ArmI64x2Mul)                   \
   V(ArmI64x2ShrU)                  \
   V(ArmI64x2BitMask)               \
+  V(ArmI64x2Eq)                    \
   V(ArmI32x4Splat)                 \
   V(ArmI32x4ExtractLane)           \
   V(ArmI32x4ReplaceLane)           \

src/compiler/backend/arm/instruction-scheduler-arm.cc

@@ -163,6 +163,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kArmI64x2Mul:
     case kArmI64x2ShrU:
     case kArmI64x2BitMask:
+    case kArmI64x2Eq:
     case kArmI32x4Splat:
     case kArmI32x4ExtractLane:
     case kArmI32x4ReplaceLane:

src/compiler/backend/arm/instruction-selector-arm.cc

@@ -2592,6 +2592,7 @@ void InstructionSelector::VisitWord32AtomicPairCompareExchange(Node* node) {
   V(I32x4MinS, kArmI32x4MinS)                         \
   V(I32x4MaxS, kArmI32x4MaxS)                         \
   V(I32x4Eq, kArmI32x4Eq)                             \
+  V(I64x2Eq, kArmI64x2Eq)                             \
   V(I32x4Ne, kArmI32x4Ne)                             \
   V(I32x4GtS, kArmI32x4GtS)                           \
   V(I32x4GeS, kArmI32x4GeS)                           \

src/compiler/backend/instruction-selector.cc

@@ -2732,10 +2732,10 @@ void InstructionSelector::VisitF32x4Qfms(Node* node) { UNIMPLEMENTED(); }
 #endif  // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_S390X
 
 #if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_S390X && !V8_TARGET_ARCH_ARM64 && \
-    !V8_TARGET_ARCH_IA32
+    !V8_TARGET_ARCH_IA32 && !V8_TARGET_ARCH_ARM
 void InstructionSelector::VisitI64x2Eq(Node* node) { UNIMPLEMENTED(); }
 #endif  // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_S390X && !V8_TARGET_ARCH_ARM64
-        // && !V8_TARGET_ARCH_IA32
+        // && !V8_TARGET_ARCH_IA32 && !V8_TARGET_ARCH_ARM
 
 #if !V8_TARGET_ARCH_ARM64
 // TODO(v8:10971) Prototype i16x8.q15mulr_sat_s

test/cctest/wasm/test-run-wasm-simd.cc

@@ -1037,12 +1037,12 @@ WASM_SIMD_TEST(I64x2Sub) {
 }
 
 #if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_S390X || \
-    V8_TARGET_ARCH_IA32
+    V8_TARGET_ARCH_IA32 || V8_TARGET_ARCH_ARM
 WASM_SIMD_TEST_NO_LOWERING(I64x2Eq) {
   RunI64x2BinOpTest(execution_tier, lower_simd, kExprI64x2Eq, Equal);
 }
 #endif  // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_S390X ||
-        // V8_TARGET_ARCH_IA32
+        // V8_TARGET_ARCH_IA32 || V8_TARGET_ARCH_ARM
 
 WASM_SIMD_TEST(F64x2Splat) {
   WasmRunner<int32_t, double> r(execution_tier, lower_simd);