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Commit f74d2a90 authored by Zhao Jiazhong's avatar Zhao Jiazhong Committed by Commit Bot
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[mips64][wasm-simd] Fix bugs of some wasm-simd operations. 

Due to lack of testing environment before, there are some bugs in the
implementations of wasm-simd on mips64 platform, this CL fix them
according to the test on Loongson 3A4000.

Change-Id: I59ab6315987fc94a06cf0bf23754f5c593879532
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2162416
Commit-Queue: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Reviewed-by: 's avatarZhi An Ng <zhin@chromium.org>
Reviewed-by: 's avatarDeepti Gandluri <gdeepti@chromium.org>
Cr-Commit-Position: refs/heads/master@{#67413}
parent 74e93186
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Showing with 242 additions and 67 deletions
src/codegen/mips64/register-mips64.h
View file @ f74d2a90
......@@ -296,11 +296,13 @@ constexpr Register cp = s7;
constexpr Register kScratchReg = s3;
constexpr Register kScratchReg2 = s4;
constexpr DoubleRegister kScratchDoubleReg = f30;
// FPU zero reg is often used to hold 0.0, but it's not hardwired to 0.0.
constexpr DoubleRegister kDoubleRegZero = f28;
// Used on mips64r6 for compare operations.
// We use the last non-callee saved odd register for N64 ABI
constexpr DoubleRegister kDoubleCompareReg = f23;
// MSA zero and scratch regs must have the same numbers as FPU zero and scratch
// MSA zero reg is often used to hold 0, but it's not hardwired to 0.
constexpr Simd128Register kSimd128RegZero = w28;
constexpr Simd128Register kSimd128ScratchReg = w30;
......
src/compiler/backend/mips64/code-generator-mips64.cc
View file @ f74d2a90
......@@ -1893,6 +1893,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
case kMips64I16x8Load8x8U: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
Simd128Register dst = i.OutputSimd128Register();
__ xor_v(kSimd128RegZero, kSimd128RegZero, kSimd128RegZero);
__ Ld(kScratchReg, i.MemoryOperand());
__ fill_d(dst, kScratchReg);
__ ilvr_b(dst, kSimd128RegZero, dst);
......@@ -1911,6 +1912,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
case kMips64I32x4Load16x4U: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
Simd128Register dst = i.OutputSimd128Register();
__ xor_v(kSimd128RegZero, kSimd128RegZero, kSimd128RegZero);
__ Ld(kScratchReg, i.MemoryOperand());
__ fill_d(dst, kScratchReg);
__ ilvr_h(dst, kSimd128RegZero, dst);
......@@ -1929,6 +1931,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
case kMips64I64x2Load32x2U: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
Simd128Register dst = i.OutputSimd128Register();
__ xor_v(kSimd128RegZero, kSimd128RegZero, kSimd128RegZero);
__ Ld(kScratchReg, i.MemoryOperand());
__ fill_d(dst, kScratchReg);
__ ilvr_w(dst, kSimd128RegZero, dst);
......@@ -2158,12 +2161,50 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
}
case kMips64F64x2Min: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
ASSEMBLE_F64X2_ARITHMETIC_BINOP(fmin_d);
Simd128Register dst = i.OutputSimd128Register();
Simd128Register src0 = i.InputSimd128Register(0);
Simd128Register src1 = i.InputSimd128Register(1);
Simd128Register scratch0 = kSimd128RegZero;
Simd128Register scratch1 = kSimd128ScratchReg;
// MSA follows IEEE 754-2008 comparision rules:
// 1. All NaN-related comparsions get false.
// 2. +0.0 equals to -0.0.
// If inputs are -0.0. and +0.0, then write -0.0 to scratch1.
// scratch1 = (src0 == src1) ? (src0 | src1) : (src1 | src1).
__ fseq_d(scratch0, src0, src1);
__ bsel_v(scratch0, src1, src0);
__ or_v(scratch1, scratch0, src1);
// scratch0 = isNaN(src0) ? src0 : scratch1.
__ fseq_d(scratch0, src0, src0);
__ bsel_v(scratch0, src0, scratch1);
// dst = (src0 < scratch0) ? src0 : scratch0.
__ fslt_d(dst, src0, scratch0);
__ bsel_v(dst, scratch0, src0);
break;
}
case kMips64F64x2Max: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
ASSEMBLE_F64X2_ARITHMETIC_BINOP(fmax_d);
Simd128Register dst = i.OutputSimd128Register();
Simd128Register src0 = i.InputSimd128Register(0);
Simd128Register src1 = i.InputSimd128Register(1);
Simd128Register scratch0 = kSimd128RegZero;
Simd128Register scratch1 = kSimd128ScratchReg;
// MSA follows IEEE 754-2008 comparision rules:
// 1. All NaN-related comparsions get false.
// 2. +0.0 equals to -0.0.
// If inputs are -0.0. and +0.0, then write +0.0 to scratch1.
// scratch1 = (src0 == src1) ? (src0 & src1) : (src1 & src1).
__ fseq_d(scratch0, src0, src1);
__ bsel_v(scratch0, src1, src0);
__ and_v(scratch1, scratch0, src1);
// scratch0 = isNaN(src0) ? src0 : scratch1.
__ fseq_d(scratch0, src0, src0);
__ bsel_v(scratch0, src0, scratch1);
// dst = (scratch0 < src0) ? src0 : scratch0.
__ fslt_d(dst, scratch0, src0);
__ bsel_v(dst, scratch0, src0);
break;
}
case kMips64F64x2Eq: {
......@@ -2174,7 +2215,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
}
case kMips64F64x2Ne: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ fcne_d(i.OutputSimd128Register(), i.InputSimd128Register(0),
__ fcune_d(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
......@@ -2206,10 +2247,10 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
if (src != dst) {
__ Move(kScratchReg, i.InputDoubleRegister(2));
if (dst != src) {
__ move_v(dst, src);
}
__ Move(kScratchReg, i.InputDoubleRegister(2));
__ insert_d(dst, i.InputInt8(1), kScratchReg);
break;
}
......@@ -2261,20 +2302,38 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
}
case kMips64I64x2Shl: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
if (instr->InputAt(1)->IsRegister()) {
__ fill_d(kSimd128ScratchReg, i.InputRegister(1));
__ sll_d(i.OutputSimd128Register(), i.InputSimd128Register(0),
kSimd128ScratchReg);
} else {
__ slli_d(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputInt6(1));
}
break;
}
case kMips64I64x2ShrS: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
if (instr->InputAt(1)->IsRegister()) {
__ fill_d(kSimd128ScratchReg, i.InputRegister(1));
__ sra_d(i.OutputSimd128Register(), i.InputSimd128Register(0),
kSimd128ScratchReg);
} else {
__ srai_d(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputInt6(1));
}
break;
}
case kMips64I64x2ShrU: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
if (instr->InputAt(1)->IsRegister()) {
__ fill_d(kSimd128ScratchReg, i.InputRegister(1));
__ srl_d(i.OutputSimd128Register(), i.InputSimd128Register(0),
kSimd128ScratchReg);
} else {
__ srli_d(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputInt6(1));
}
break;
}
case kMips64F32x4Splat: {
......@@ -2293,10 +2352,10 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
Simd128Register src = i.InputSimd128Register(0);
Simd128Register dst = i.OutputSimd128Register();
if (src != dst) {
__ FmoveLow(kScratchReg, i.InputSingleRegister(2));
if (dst != src) {
__ move_v(dst, src);
}
__ FmoveLow(kScratchReg, i.InputSingleRegister(2));
__ insert_w(dst, i.InputInt8(1), kScratchReg);
break;
}
......@@ -2343,20 +2402,38 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
}
case kMips64I32x4Shl: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
if (instr->InputAt(1)->IsRegister()) {
__ fill_w(kSimd128ScratchReg, i.InputRegister(1));
__ sll_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
kSimd128ScratchReg);
} else {
__ slli_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputInt5(1));
}
break;
}
case kMips64I32x4ShrS: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
if (instr->InputAt(1)->IsRegister()) {
__ fill_w(kSimd128ScratchReg, i.InputRegister(1));
__ sra_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
kSimd128ScratchReg);
} else {
__ srai_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputInt5(1));
}
break;
}
case kMips64I32x4ShrU: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
if (instr->InputAt(1)->IsRegister()) {
__ fill_w(kSimd128ScratchReg, i.InputRegister(1));
__ srl_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
kSimd128ScratchReg);
} else {
__ srli_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputInt5(1));
}
break;
}
case kMips64I32x4MaxU: {
......@@ -2380,9 +2457,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
}
case kMips64S128AndNot: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
Simd128Register dst = i.OutputSimd128Register();
__ nor_v(dst, i.InputSimd128Register(1), i.InputSimd128Register(1));
__ and_v(dst, dst, i.InputSimd128Register(0));
Simd128Register scratch = kSimd128ScratchReg,
dst = i.OutputSimd128Register(),
src0 = i.InputSimd128Register(0),
src1 = i.InputSimd128Register(1);
__ nor_v(scratch, src1, src1);
__ and_v(dst, scratch, src0);
break;
}
case kMips64F32x4Abs: {
......@@ -2431,14 +2511,50 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
}
case kMips64F32x4Max: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ fmax_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
Simd128Register dst = i.OutputSimd128Register();
Simd128Register src0 = i.InputSimd128Register(0);
Simd128Register src1 = i.InputSimd128Register(1);
Simd128Register scratch0 = kSimd128RegZero;
Simd128Register scratch1 = kSimd128ScratchReg;
// MSA follows IEEE 754-2008 comparision rules:
// 1. All NaN-related comparsions get false.
// 2. +0.0 equals to -0.0.
// If inputs are -0.0. and +0.0, then write +0.0 to scratch1.
// scratch1 = (src0 == src1) ? (src0 & src1) : (src1 & src1).
__ fseq_w(scratch0, src0, src1);
__ bsel_v(scratch0, src1, src0);
__ and_v(scratch1, scratch0, src1);
// scratch0 = isNaN(src0) ? src0 : scratch1.
__ fseq_w(scratch0, src0, src0);
__ bsel_v(scratch0, src0, scratch1);
// dst = (scratch0 < src0) ? src0 : scratch0.
__ fslt_w(dst, scratch0, src0);
__ bsel_v(dst, scratch0, src0);
break;
}
case kMips64F32x4Min: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ fmin_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
Simd128Register dst = i.OutputSimd128Register();
Simd128Register src0 = i.InputSimd128Register(0);
Simd128Register src1 = i.InputSimd128Register(1);
Simd128Register scratch0 = kSimd128RegZero;
Simd128Register scratch1 = kSimd128ScratchReg;
// MSA follows IEEE 754-2008 comparision rules:
// 1. All NaN-related comparsions get false.
// 2. +0.0 equals to -0.0.
// If inputs are -0.0. and +0.0, then write -0.0 to scratch1.
// scratch1 = (src0 == src1) ? (src0 | src1) : (src1 | src1).
__ fseq_w(scratch0, src0, src1);
__ bsel_v(scratch0, src1, src0);
__ or_v(scratch1, scratch0, src1);
// scratch0 = isNaN(src0) ? src0 : scratch1.
__ fseq_w(scratch0, src0, src0);
__ bsel_v(scratch0, src0, scratch1);
// dst = (src0 < scratch0) ? src0 : scratch0.
__ fslt_w(dst, src0, scratch0);
__ bsel_v(dst, scratch0, src0);
break;
}
case kMips64F32x4Eq: {
......@@ -2449,7 +2565,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
}
case kMips64F32x4Ne: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ fcne_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
__ fcune_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1));
break;
}
......@@ -2513,6 +2629,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
}
case kMips64I32x4Abs: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ xor_v(kSimd128RegZero, kSimd128RegZero, kSimd128RegZero);
__ asub_s_w(i.OutputSimd128Register(), i.InputSimd128Register(0),
kSimd128RegZero);
break;
......@@ -2553,20 +2670,38 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
}
case kMips64I16x8Shl: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
if (instr->InputAt(1)->IsRegister()) {
__ fill_h(kSimd128ScratchReg, i.InputRegister(1));
__ sll_h(i.OutputSimd128Register(), i.InputSimd128Register(0),
kSimd128ScratchReg);
} else {
__ slli_h(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputInt4(1));
}
break;
}
case kMips64I16x8ShrS: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
if (instr->InputAt(1)->IsRegister()) {
__ fill_h(kSimd128ScratchReg, i.InputRegister(1));
__ sra_h(i.OutputSimd128Register(), i.InputSimd128Register(0),
kSimd128ScratchReg);
} else {
__ srai_h(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputInt4(1));
}
break;
}
case kMips64I16x8ShrU: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
if (instr->InputAt(1)->IsRegister()) {
__ fill_h(kSimd128ScratchReg, i.InputRegister(1));
__ srl_h(i.OutputSimd128Register(), i.InputSimd128Register(0),
kSimd128ScratchReg);
} else {
__ srli_h(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputInt4(1));
}
break;
}
case kMips64I16x8Add: {
......@@ -2680,6 +2815,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
}
case kMips64I16x8Abs: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ xor_v(kSimd128RegZero, kSimd128RegZero, kSimd128RegZero);
__ asub_s_h(i.OutputSimd128Register(), i.InputSimd128Register(0),
kSimd128RegZero);
break;
......@@ -2720,14 +2856,26 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
}
case kMips64I8x16Shl: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
if (instr->InputAt(1)->IsRegister()) {
__ fill_b(kSimd128ScratchReg, i.InputRegister(1));
__ sll_b(i.OutputSimd128Register(), i.InputSimd128Register(0),
kSimd128ScratchReg);
} else {
__ slli_b(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputInt3(1));
}
break;
}
case kMips64I8x16ShrS: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
if (instr->InputAt(1)->IsRegister()) {
__ fill_b(kSimd128ScratchReg, i.InputRegister(1));
__ sra_b(i.OutputSimd128Register(), i.InputSimd128Register(0),
kSimd128ScratchReg);
} else {
__ srai_b(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputInt3(1));
}
break;
}
case kMips64I8x16Add: {
......@@ -2799,8 +2947,14 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
}
case kMips64I8x16ShrU: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
if (instr->InputAt(1)->IsRegister()) {
__ fill_b(kSimd128ScratchReg, i.InputRegister(1));
__ srl_b(i.OutputSimd128Register(), i.InputSimd128Register(0),
kSimd128ScratchReg);
} else {
__ srli_b(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputInt3(1));
}
break;
}
case kMips64I8x16AddSaturateU: {
......@@ -2847,6 +3001,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
}
case kMips64I8x16Abs: {
CpuFeatureScope msa_scope(tasm(), MIPS_SIMD);
__ xor_v(kSimd128RegZero, kSimd128RegZero, kSimd128RegZero);
__ asub_s_b(i.OutputSimd128Register(), i.InputSimd128Register(0),
kSimd128RegZero);
break;
......@@ -2884,7 +3039,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ BranchMSA(&all_false, MSA_BRANCH_V, all_zero,
i.InputSimd128Register(0), USE_DELAY_SLOT);
__ li(dst, 0l); // branch delay slot
__ li(dst, -1);
__ li(dst, 1);
__ bind(&all_false);
break;
}
......@@ -2894,7 +3049,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
Label all_true;
__ BranchMSA(&all_true, MSA_BRANCH_W, all_not_zero,
i.InputSimd128Register(0), USE_DELAY_SLOT);
__ li(dst, -1); // branch delay slot
__ li(dst, 1); // branch delay slot
__ li(dst, 0l);
__ bind(&all_true);
break;
......@@ -2905,7 +3060,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
Label all_true;
__ BranchMSA(&all_true, MSA_BRANCH_H, all_not_zero,
i.InputSimd128Register(0), USE_DELAY_SLOT);
__ li(dst, -1); // branch delay slot
__ li(dst, 1); // branch delay slot
__ li(dst, 0l);
__ bind(&all_true);
break;
......@@ -2916,7 +3071,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
Label all_true;
__ BranchMSA(&all_true, MSA_BRANCH_B, all_not_zero,
i.InputSimd128Register(0), USE_DELAY_SLOT);
__ li(dst, -1); // branch delay slot
__ li(dst, 1); // branch delay slot
__ li(dst, 0l);
__ bind(&all_true);
break;
......@@ -3217,9 +3372,9 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
ctl = i.InputSimd128Register(1);
DCHECK(dst != ctl && dst != tbl);
Simd128Register zeroReg = i.TempSimd128Register(0);
__ fill_d(zeroReg, zero_reg);
__ xor_v(zeroReg, zeroReg, zeroReg);
__ move_v(dst, ctl);
__ vshf_b(dst, tbl, zeroReg);
__ vshf_b(dst, zeroReg, tbl);
break;
}
case kMips64S8x8Reverse: {
......@@ -3311,9 +3466,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
Simd128Register dst = i.OutputSimd128Register();
Simd128Register src0 = i.InputSimd128Register(0);
Simd128Register src1 = i.InputSimd128Register(1);
__ sat_u_w(kSimd128ScratchReg, src0, 15);
__ sat_u_w(kSimd128RegZero, src1, 15); // kSimd128RegZero as scratch
__ pckev_h(dst, kSimd128RegZero, kSimd128ScratchReg);
__ xor_v(kSimd128RegZero, kSimd128RegZero, kSimd128RegZero);
__ max_s_w(kSimd128ScratchReg, kSimd128RegZero, src0);
__ sat_u_w(kSimd128ScratchReg, kSimd128ScratchReg, 15);
__ max_s_w(dst, kSimd128RegZero, src1);
__ sat_u_w(dst, dst, 15);
__ pckev_h(dst, dst, kSimd128ScratchReg);
break;
}
case kMips64I16x8UConvertI8x16Low: {
......@@ -3345,9 +3503,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
Simd128Register dst = i.OutputSimd128Register();
Simd128Register src0 = i.InputSimd128Register(0);
Simd128Register src1 = i.InputSimd128Register(1);
__ sat_u_h(kSimd128ScratchReg, src0, 7);
__ sat_u_h(kSimd128RegZero, src1, 7); // kSimd128RegZero as scratch
__ pckev_b(dst, kSimd128RegZero, kSimd128ScratchReg);
__ xor_v(kSimd128RegZero, kSimd128RegZero, kSimd128RegZero);
__ max_s_h(kSimd128ScratchReg, kSimd128RegZero, src0);
__ sat_u_h(kSimd128ScratchReg, kSimd128ScratchReg, 7);
__ max_s_h(dst, kSimd128RegZero, src1);
__ sat_u_h(dst, dst, 7);
__ pckev_b(dst, dst, kSimd128ScratchReg);
break;
}
case kMips64F32x4AddHoriz: {
......
src/compiler/backend/mips64/instruction-selector-mips64.cc
View file @ f74d2a90
......@@ -132,6 +132,20 @@ static void VisitRRI(InstructionSelector* selector, ArchOpcode opcode,
g.UseRegister(node->InputAt(0)), g.UseImmediate(imm));
}
static void VisitSimdShift(InstructionSelector* selector, ArchOpcode opcode,
Node* node) {
Mips64OperandGenerator g(selector);
if (g.IsIntegerConstant(node->InputAt(1))) {
selector->Emit(opcode, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)),
g.UseImmediate(node->InputAt(1)));
} else {
selector->Emit(opcode, g.DefineAsRegister(node),
g.UseRegister(node->InputAt(0)),
g.UseRegister(node->InputAt(1)));
}
}
static void VisitRRIR(InstructionSelector* selector, ArchOpcode opcode,
Node* node) {
Mips64OperandGenerator g(selector);
......@@ -2877,7 +2891,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
void InstructionSelector::VisitS128Zero(Node* node) {
Mips64OperandGenerator g(this);
Emit(kMips64S128Zero, g.DefineSameAsFirst(node));
Emit(kMips64S128Zero, g.DefineAsRegister(node));
}
#define SIMD_VISIT_SPLAT(Type) \
......@@ -2917,7 +2931,7 @@ SIMD_UNOP_LIST(SIMD_VISIT_UNOP)
#define SIMD_VISIT_SHIFT_OP(Name) \
void InstructionSelector::Visit##Name(Node* node) { \
VisitRRI(this, kMips64##Name, node); \
VisitSimdShift(this, kMips64##Name, node); \
}
SIMD_SHIFT_OP_LIST(SIMD_VISIT_SHIFT_OP)
#undef SIMD_VISIT_SHIFT_OP
......
src/wasm/baseline/mips64/liftoff-assembler-mips64.h
View file @ f74d2a90
......@@ -62,7 +62,7 @@ inline void Load(LiftoffAssembler* assm, LiftoffRegister dst, MemOperand src,
assm->Ldc1(dst.fp(), src);
break;
case ValueType::kS128:
assm->ld_d(dst.fp().toW(), src);
assm->ld_b(dst.fp().toW(), src);
break;
default:
UNREACHABLE();
......@@ -109,7 +109,7 @@ inline void push(LiftoffAssembler* assm, LiftoffRegister reg, ValueType type) {
break;
case ValueType::kS128:
assm->daddiu(sp, sp, -kSystemPointerSize * 2);
assm->st_d(reg.fp().toW(), MemOperand(sp, 0));
assm->st_b(reg.fp().toW(), MemOperand(sp, 0));
break;
default:
UNREACHABLE();
......@@ -382,7 +382,7 @@ void LiftoffAssembler::Load(LiftoffRegister dst, Register src_addr,
TurboAssembler::Uldc1(dst.fp(), src_op, t8);
break;
case LoadType::kS128Load:
TurboAssembler::ld_d(dst.fp().toW(), src_op);
TurboAssembler::ld_b(dst.fp().toW(), src_op);
break;
default:
UNREACHABLE();
......@@ -448,7 +448,7 @@ void LiftoffAssembler::Store(Register dst_addr, Register offset_reg,
TurboAssembler::Usdc1(src.fp(), dst_op, t8);
break;
case StoreType::kS128Store:
TurboAssembler::st_d(src.fp().toW(), dst_op);
TurboAssembler::st_b(src.fp().toW(), dst_op);
break;
default:
UNREACHABLE();
......@@ -561,7 +561,7 @@ void LiftoffAssembler::Spill(int offset, LiftoffRegister reg, ValueType type) {
TurboAssembler::Sdc1(reg.fp(), dst);
break;
case ValueType::kS128:
TurboAssembler::st_d(reg.fp().toW(), dst);
TurboAssembler::st_b(reg.fp().toW(), dst);
break;
default:
UNREACHABLE();
......@@ -607,7 +607,7 @@ void LiftoffAssembler::Fill(LiftoffRegister reg, int offset, ValueType type) {
TurboAssembler::Ldc1(reg.fp(), src);
break;
case ValueType::kS128:
TurboAssembler::ld_d(reg.fp().toW(), src);
TurboAssembler::ld_b(reg.fp().toW(), src);
break;
default:
UNREACHABLE();
......
test/cctest/wasm/test-run-wasm-simd.cc
View file @ f74d2a90
......@@ -1215,7 +1215,8 @@ WASM_SIMD_TEST_NO_LOWERING(F64x2ReplaceLane) {
CHECK_EQ(1., ReadLittleEndianValue<double>(&g1[1]));
}
#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_S390X
#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_S390X || \
V8_TARGET_ARCH_MIPS64
WASM_SIMD_TEST_NO_LOWERING(F64x2ExtractLaneWithI64x2) {
WasmRunner<int64_t> r(execution_tier, lower_simd);
BUILD_V(r, WASM_IF_ELSE_L(
......@@ -1235,7 +1236,8 @@ WASM_SIMD_TEST_NO_LOWERING(I64x2ExtractWithF64x2) {
WASM_I64V(1), WASM_I64V(0)));
CHECK_EQ(1, r.Call());
}
#endif // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_S390X
#endif // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_S390X ||
// V8_TARGET_ARCH_MIPS64
bool IsExtreme(double x) {
double abs_x = std::fabs(x);
......@@ -3555,8 +3557,6 @@ WASM_SIMD_TEST_NO_LOWERING(I64x2Load32x2S) {
kExprI64x2Load32x2S);
}
#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_IA32 || V8_TARGET_ARCH_ARM64 || \
V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_S390X
#define WASM_SIMD_ANYTRUE_TEST(format, lanes, max, param_type) \
WASM_SIMD_TEST(S##format##AnyTrue) { \
FLAG_SCOPE(wasm_simd_post_mvp); \
......@@ -3598,8 +3598,6 @@ WASM_SIMD_ALLTRUE_TEST(64x2, 2, 0xffffffffffffffff, int64_t)
WASM_SIMD_ALLTRUE_TEST(32x4, 4, 0xffffffff, int32_t)
WASM_SIMD_ALLTRUE_TEST(16x8, 8, 0xffff, int32_t)
WASM_SIMD_ALLTRUE_TEST(8x16, 16, 0xff, int32_t)
#endif // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_IA32 || V8_TARGET_ARCH_ARM64 ||
// V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_S390X
WASM_SIMD_TEST(BitSelect) {
WasmRunner<int32_t, int32_t> r(execution_tier, lower_simd);
......
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