[ptr-compr][arm64] Use correct immediate range for kArchStoreWithBarrier.

With compressed pointers, `kArchStoreWithBarrier` is a 32-bit store instead of
64-bit, and this means the index has a differerent immediate range.

Bug: v8:7703
Change-Id: If61c8544b0da87ba2779ba2c1a6963b52e3e5d9a
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1710674
Commit-Queue: Sigurd Schneider <sigurds@chromium.org>
Reviewed-by: Sigurd Schneider <sigurds@chromium.org>
Cr-Commit-Position: refs/heads/master@{#62861}

src/compiler/backend/arm64/instruction-selector-arm64.cc

@@ -679,7 +679,8 @@ void InstructionSelector::VisitStore(Node* node) {
     // OutOfLineRecordWrite uses the index in an add or sub instruction, but we
     // can trust the assembler to generate extra instructions if the index does
     // not fit into add or sub. So here only check the immediate for a store.
-    if (g.CanBeImmediate(index, kLoadStoreImm64)) {
+    if (g.CanBeImmediate(index, COMPRESS_POINTERS_BOOL ? kLoadStoreImm32
+                                                       : kLoadStoreImm64)) {
       inputs[input_count++] = g.UseImmediate(index);
       addressing_mode = kMode_MRI;
     } else {

test/unittests/compiler/arm64/instruction-selector-arm64-unittest.cc

@@ -2887,7 +2887,13 @@ TEST_P(InstructionSelectorStoreWithBarrierTest,
     // We have two instructions that are not nops: Store and Return.
     ASSERT_EQ(2U, s.size());
     EXPECT_EQ(kArchStoreWithWriteBarrier, s[0]->arch_opcode());
-    EXPECT_EQ(kMode_MRI, s[0]->addressing_mode());
+    // With compressed pointers, a store with barrier is a 32-bit str which has
+    // a smaller immediate range.
+    if (COMPRESS_POINTERS_BOOL && (index > 16380)) {
+      EXPECT_EQ(kMode_MRR, s[0]->addressing_mode());
+    } else {
+      EXPECT_EQ(kMode_MRI, s[0]->addressing_mode());
+    }
     EXPECT_EQ(3U, s[0]->InputCount());
     EXPECT_EQ(0U, s[0]->OutputCount());
   }