Commit f5b6886d authored by Dusan Simicic's avatar Dusan Simicic Committed by Commit Bot

MIPS[64]: Implement AddHoriz SIMD operations

Add support for F32x4AddHoriz, I32x4AddHoriz, I16x8AddHoriz
operations for mips32 and mips64 architectures.

Bug: 
Change-Id: I5a40f23677418ffd81d4d5229203a439545575b8
Reviewed-on: https://chromium-review.googlesource.com/518016
Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
Reviewed-by: 's avatarBenedikt Meurer <bmeurer@chromium.org>
Reviewed-by: 's avatarMircea Trofin <mtrofin@chromium.org>
Reviewed-by: 's avatarBill Budge <bbudge@chromium.org>
Reviewed-by: 's avatarMiran Karić <Miran.Karic@imgtec.com>
Reviewed-by: 's avatarIvica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
Cr-Commit-Position: refs/heads/master@{#46272}
parent c784d62b
......@@ -2070,15 +2070,9 @@ void InstructionSelector::VisitF32x4RecipSqrtApprox(Node* node) {
}
void InstructionSelector::VisitF32x4Add(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_MIPS
// && !V8_TARGET_ARCH_MIPS64
#if !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64
void InstructionSelector::VisitF32x4AddHoriz(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64
#if !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_MIPS && \
!V8_TARGET_ARCH_MIPS64
void InstructionSelector::VisitF32x4Sub(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF32x4Mul(Node* node) { UNIMPLEMENTED(); }
......@@ -2138,9 +2132,11 @@ void InstructionSelector::VisitI32x4ShrU(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_X64
// && !V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_MIPS64
#if !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_X64
#if !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_X64 && \
!V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_MIPS64
void InstructionSelector::VisitI32x4AddHoriz(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_X64
// && !V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_MIPS64
#if !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_MIPS && \
!V8_TARGET_ARCH_MIPS64
......@@ -2228,9 +2224,11 @@ void InstructionSelector::VisitI16x8SubSaturateS(Node* node) {
#endif // !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_X64
// && !V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_MIPS64
#if !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_X64
#if !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_X64 && \
!V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_MIPS64
void InstructionSelector::VisitI16x8AddHoriz(Node* node) { UNIMPLEMENTED(); }
#endif // !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_X64
// && !V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_MIPS64
#if !V8_TARGET_ARCH_ARM && !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_X64 && \
!V8_TARGET_ARCH_MIPS && !V8_TARGET_ARCH_MIPS64
......
......@@ -2672,6 +2672,38 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ pckev_b(dst, kSimd128RegZero, kSimd128ScratchReg);
break;
}
case kMipsF32x4AddHoriz: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
Simd128Register src0 = i.InputSimd128Register(0);
Simd128Register src1 = i.InputSimd128Register(1);
Simd128Register dst = i.OutputSimd128Register();
__ shf_w(kSimd128ScratchReg, src0, 0xB1); // 2 3 0 1 : 10110001 : 0xB1
__ shf_w(kSimd128RegZero, src1, 0xB1); // kSimd128RegZero as scratch
__ fadd_w(kSimd128ScratchReg, kSimd128ScratchReg, src0);
__ fadd_w(kSimd128RegZero, kSimd128RegZero, src1);
__ pckev_w(dst, kSimd128RegZero, kSimd128ScratchReg);
break;
}
case kMipsI32x4AddHoriz: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
Simd128Register src0 = i.InputSimd128Register(0);
Simd128Register src1 = i.InputSimd128Register(1);
Simd128Register dst = i.OutputSimd128Register();
__ hadd_s_d(kSimd128ScratchReg, src0, src0);
__ hadd_s_d(kSimd128RegZero, src1, src1); // kSimd128RegZero as scratch
__ pckev_w(dst, kSimd128RegZero, kSimd128ScratchReg);
break;
}
case kMipsI16x8AddHoriz: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
Simd128Register src0 = i.InputSimd128Register(0);
Simd128Register src1 = i.InputSimd128Register(1);
Simd128Register dst = i.OutputSimd128Register();
__ hadd_s_w(kSimd128ScratchReg, src0, src0);
__ hadd_s_w(kSimd128RegZero, src1, src1); // kSimd128RegZero as scratch
__ pckev_h(dst, kSimd128RegZero, kSimd128ScratchReg);
break;
}
}
return kSuccess;
} // NOLINT(readability/fn_size)
......
......@@ -138,6 +138,7 @@ namespace compiler {
V(MipsI32x4ExtractLane) \
V(MipsI32x4ReplaceLane) \
V(MipsI32x4Add) \
V(MipsI32x4AddHoriz) \
V(MipsI32x4Sub) \
V(MipsF32x4Splat) \
V(MipsF32x4ExtractLane) \
......@@ -159,6 +160,7 @@ namespace compiler {
V(MipsF32x4RecipApprox) \
V(MipsF32x4RecipSqrtApprox) \
V(MipsF32x4Add) \
V(MipsF32x4AddHoriz) \
V(MipsF32x4Sub) \
V(MipsF32x4Mul) \
V(MipsF32x4Max) \
......@@ -183,6 +185,7 @@ namespace compiler {
V(MipsI16x8ShrU) \
V(MipsI16x8Add) \
V(MipsI16x8AddSaturateS) \
V(MipsI16x8AddHoriz) \
V(MipsI16x8Sub) \
V(MipsI16x8SubSaturateS) \
V(MipsI16x8Mul) \
......
......@@ -1986,6 +1986,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
#define SIMD_BINOP_LIST(V) \
V(F32x4Add, kMipsF32x4Add) \
V(F32x4AddHoriz, kMipsF32x4AddHoriz) \
V(F32x4Sub, kMipsF32x4Sub) \
V(F32x4Mul, kMipsF32x4Mul) \
V(F32x4Max, kMipsF32x4Max) \
......@@ -1995,6 +1996,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(F32x4Lt, kMipsF32x4Lt) \
V(F32x4Le, kMipsF32x4Le) \
V(I32x4Add, kMipsI32x4Add) \
V(I32x4AddHoriz, kMipsI32x4AddHoriz) \
V(I32x4Sub, kMipsI32x4Sub) \
V(I32x4Mul, kMipsI32x4Mul) \
V(I32x4MaxS, kMipsI32x4MaxS) \
......@@ -2010,6 +2012,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I16x8Add, kMipsI16x8Add) \
V(I16x8AddSaturateS, kMipsI16x8AddSaturateS) \
V(I16x8AddSaturateU, kMipsI16x8AddSaturateU) \
V(I16x8AddHoriz, kMipsI16x8AddHoriz) \
V(I16x8Sub, kMipsI16x8Sub) \
V(I16x8SubSaturateS, kMipsI16x8SubSaturateS) \
V(I16x8SubSaturateU, kMipsI16x8SubSaturateU) \
......
......@@ -2991,6 +2991,38 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ pckev_b(dst, kSimd128RegZero, kSimd128ScratchReg);
break;
}
case kMips64F32x4AddHoriz: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
Simd128Register src0 = i.InputSimd128Register(0);
Simd128Register src1 = i.InputSimd128Register(1);
Simd128Register dst = i.OutputSimd128Register();
__ shf_w(kSimd128ScratchReg, src0, 0xB1); // 2 3 0 1 : 10110001 : 0xB1
__ shf_w(kSimd128RegZero, src1, 0xB1); // kSimd128RegZero as scratch
__ fadd_w(kSimd128ScratchReg, kSimd128ScratchReg, src0);
__ fadd_w(kSimd128RegZero, kSimd128RegZero, src1);
__ pckev_w(dst, kSimd128RegZero, kSimd128ScratchReg);
break;
}
case kMips64I32x4AddHoriz: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
Simd128Register src0 = i.InputSimd128Register(0);
Simd128Register src1 = i.InputSimd128Register(1);
Simd128Register dst = i.OutputSimd128Register();
__ hadd_s_d(kSimd128ScratchReg, src0, src0);
__ hadd_s_d(kSimd128RegZero, src1, src1); // kSimd128RegZero as scratch
__ pckev_w(dst, kSimd128RegZero, kSimd128ScratchReg);
break;
}
case kMips64I16x8AddHoriz: {
CpuFeatureScope msa_scope(masm(), MIPS_SIMD);
Simd128Register src0 = i.InputSimd128Register(0);
Simd128Register src1 = i.InputSimd128Register(1);
Simd128Register dst = i.OutputSimd128Register();
__ hadd_s_w(kSimd128ScratchReg, src0, src0);
__ hadd_s_w(kSimd128RegZero, src1, src1); // kSimd128RegZero as scratch
__ pckev_h(dst, kSimd128RegZero, kSimd128ScratchReg);
break;
}
}
return kSuccess;
} // NOLINT(readability/fn_size)
......
......@@ -172,6 +172,7 @@ namespace compiler {
V(Mips64I32x4ExtractLane) \
V(Mips64I32x4ReplaceLane) \
V(Mips64I32x4Add) \
V(Mips64I32x4AddHoriz) \
V(Mips64I32x4Sub) \
V(Mips64F32x4Splat) \
V(Mips64F32x4ExtractLane) \
......@@ -193,6 +194,7 @@ namespace compiler {
V(Mips64F32x4RecipApprox) \
V(Mips64F32x4RecipSqrtApprox) \
V(Mips64F32x4Add) \
V(Mips64F32x4AddHoriz) \
V(Mips64F32x4Sub) \
V(Mips64F32x4Mul) \
V(Mips64F32x4Max) \
......@@ -217,6 +219,7 @@ namespace compiler {
V(Mips64I16x8ShrU) \
V(Mips64I16x8Add) \
V(Mips64I16x8AddSaturateS) \
V(Mips64I16x8AddHoriz) \
V(Mips64I16x8Sub) \
V(Mips64I16x8SubSaturateS) \
V(Mips64I16x8Mul) \
......
......@@ -2735,6 +2735,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
#define SIMD_BINOP_LIST(V) \
V(F32x4Add, kMips64F32x4Add) \
V(F32x4AddHoriz, kMips64F32x4AddHoriz) \
V(F32x4Sub, kMips64F32x4Sub) \
V(F32x4Mul, kMips64F32x4Mul) \
V(F32x4Max, kMips64F32x4Max) \
......@@ -2744,6 +2745,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(F32x4Lt, kMips64F32x4Lt) \
V(F32x4Le, kMips64F32x4Le) \
V(I32x4Add, kMips64I32x4Add) \
V(I32x4AddHoriz, kMips64I32x4AddHoriz) \
V(I32x4Sub, kMips64I32x4Sub) \
V(I32x4Mul, kMips64I32x4Mul) \
V(I32x4MaxS, kMips64I32x4MaxS) \
......@@ -2759,6 +2761,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(I16x8Add, kMips64I16x8Add) \
V(I16x8AddSaturateS, kMips64I16x8AddSaturateS) \
V(I16x8AddSaturateU, kMips64I16x8AddSaturateU) \
V(I16x8AddHoriz, kMips64I16x8AddHoriz) \
V(I16x8Sub, kMips64I16x8Sub) \
V(I16x8SubSaturateS, kMips64I16x8SubSaturateS) \
V(I16x8SubSaturateU, kMips64I16x8SubSaturateU) \
......
......@@ -1605,7 +1605,8 @@ void RunBinaryLaneOpTest(
#endif // V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_MIPS ||
// V8_TARGET_ARCH_MIPS64
#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_X64
#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_X64 || \
V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64
WASM_SIMD_TEST(I32x4AddHoriz) {
RunBinaryLaneOpTest<int32_t>(kExprI32x4AddHoriz, {{1, 5, 9, 13}});
}
......@@ -1614,13 +1615,16 @@ WASM_SIMD_TEST(I16x8AddHoriz) {
RunBinaryLaneOpTest<int16_t>(kExprI16x8AddHoriz,
{{1, 5, 9, 13, 17, 21, 25, 29}});
}
#endif // V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_X64
#endif // V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_X64 ||
// V8_TARGET_ARCH_MIPS || V8_TARGET_ARCH_MIPS64
#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64
#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_MIPS || \
V8_TARGET_ARCH_MIPS64
WASM_SIMD_TEST(F32x4AddHoriz) {
RunBinaryLaneOpTest<float>(kExprF32x4AddHoriz, {{1.0f, 5.0f, 9.0f, 13.0f}});
}
#endif // V8_TARGET_ARCH_ARM
#endif // V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_MIPS ||
// V8_TARGET_ARCH_MIPS64
#if V8_TARGET_ARCH_ARM || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_MIPS || \
V8_TARGET_ARCH_MIPS64
......
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