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Commit f572d69c authored by Milad Fa's avatar Milad Fa Committed by V8 LUCI CQ
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S390 [liftoff]: Implement simd any/all true ops 

Change-Id: Ia103e4010faa67daa3ebd504449e495652a55a3b
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3425098Reviewed-by: 's avatarJunliang Yan <junyan@redhat.com>
Commit-Queue: Milad Farazmand <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/main@{#78872}
parent 12066fc5
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Showing with 77 additions and 56 deletions
src/codegen/s390/macro-assembler-s390.cc
View file @ f572d69c
......@@ -5406,6 +5406,27 @@ SIMD_EXT_MUL_LIST(EMIT_SIMD_EXT_MUL)
#undef EMIT_SIMD_EXT_MUL
#undef SIMD_EXT_MUL_LIST
#define SIMD_ALL_TRUE_LIST(V) \
V(I64x2AllTrue, 3) \
V(I32x4AllTrue, 2) \
V(I16x8AllTrue, 1) \
V(I8x16AllTrue, 0)
#define EMIT_SIMD_ALL_TRUE(name, mode) \
void TurboAssembler::name(Register dst, Simd128Register src, \
Register scratch1, Simd128Register scratch2) { \
mov(scratch1, Operand(1)); \
xgr(dst, dst); \
vx(scratch2, scratch2, scratch2, Condition(0), Condition(0), \
Condition(2)); \
vceq(scratch2, src, scratch2, Condition(0), Condition(mode)); \
vtm(scratch2, scratch2, Condition(0), Condition(0), Condition(0)); \
locgr(Condition(8), dst, scratch1); \
}
SIMD_ALL_TRUE_LIST(EMIT_SIMD_ALL_TRUE)
#undef EMIT_SIMD_ALL_TRUE
#undef SIMD_ALL_TRUE_LIST
void TurboAssembler::I64x2Mul(Simd128Register dst, Simd128Register src1,
Simd128Register src2) {
Register scratch_1 = r0;
......@@ -5571,6 +5592,14 @@ void TurboAssembler::I8x16BitMask(Register dst, Simd128Register src,
vlgv(dst, scratch3, MemOperand(r0, 3), Condition(1));
}
void TurboAssembler::V128AnyTrue(Register dst, Simd128Register src,
Register scratch) {
mov(dst, Operand(1));
xgr(scratch, scratch);
vtm(src, src, Condition(0), Condition(0), Condition(0));
locgr(Condition(8), dst, scratch);
}
// Vector LE Load and Transform instructions.
#ifdef V8_TARGET_BIG_ENDIAN
#define IS_BIG_ENDIAN true
......
src/codegen/s390/macro-assembler-s390.h
View file @ f572d69c
......@@ -1113,6 +1113,7 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
Simd128Register scratch2);
void I8x16BitMask(Register dst, Simd128Register src, Register scratch1,
Register scratch2, Simd128Register scratch3);
void V128AnyTrue(Register dst, Simd128Register src, Register scratch);
#define SIMD_UNOP_LIST(V) \
V(F64x2Abs) \
......@@ -1285,6 +1286,19 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
#undef PROTOTYPE_SIMD_EXT_MUL
#undef SIMD_EXT_MUL_LIST
#define SIMD_ALL_TRUE_LIST(V) \
V(I64x2AllTrue) \
V(I32x4AllTrue) \
V(I16x8AllTrue) \
V(I8x16AllTrue)
#define PROTOTYPE_SIMD_ALL_TRUE(name) \
void name(Register dst, Simd128Register src, Register scratch1, \
Simd128Register scratch2);
SIMD_ALL_TRUE_LIST(PROTOTYPE_SIMD_ALL_TRUE)
#undef PROTOTYPE_SIMD_ALL_TRUE
#undef SIMD_ALL_TRUE_LIST
// ---------------------------------------------------------------------------
// Pointer compression Support
......
src/compiler/backend/s390/code-generator-s390.cc
View file @ f572d69c
......@@ -2764,6 +2764,22 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
#undef EMIT_SIMD_EXT_MUL
#undef SIMD_EXT_MUL_LIST
#define SIMD_ALL_TRUE_LIST(V) \
V(I64x2AllTrue) \
V(I32x4AllTrue) \
V(I16x8AllTrue) \
V(I8x16AllTrue)
#define EMIT_SIMD_ALL_TRUE(name) \
case kS390_##name: { \
__ name(i.OutputRegister(), i.InputSimd128Register(0), kScratchReg, \
kScratchDoubleReg); \
break; \
}
SIMD_ALL_TRUE_LIST(EMIT_SIMD_ALL_TRUE)
#undef EMIT_SIMD_ALL_TRUE
#undef SIMD_ALL_TRUE_LIST
// vector binops
case kS390_F64x2Qfma: {
Simd128Register src0 = i.InputSimd128Register(0);
......@@ -2832,43 +2848,10 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
}
// vector boolean unops
case kS390_V128AnyTrue: {
Simd128Register src = i.InputSimd128Register(0);
Register dst = i.OutputRegister();
__ mov(dst, Operand(1));
__ xgr(kScratchReg, kScratchReg);
__ vtm(src, src, Condition(0), Condition(0), Condition(0));
__ locgr(Condition(8), dst, kScratchReg);
break;
}
#define SIMD_ALL_TRUE(mode) \
Simd128Register src = i.InputSimd128Register(0); \
Register dst = i.OutputRegister(); \
__ mov(kScratchReg, Operand(1)); \
__ xgr(dst, dst); \
__ vx(kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg, Condition(0), \
Condition(0), Condition(2)); \
__ vceq(kScratchDoubleReg, src, kScratchDoubleReg, Condition(0), \
Condition(mode)); \
__ vtm(kScratchDoubleReg, kScratchDoubleReg, Condition(0), Condition(0), \
Condition(0)); \
__ locgr(Condition(8), dst, kScratchReg);
case kS390_I64x2AllTrue: {
SIMD_ALL_TRUE(3)
break;
}
case kS390_I32x4AllTrue: {
SIMD_ALL_TRUE(2)
break;
}
case kS390_I16x8AllTrue: {
SIMD_ALL_TRUE(1)
break;
}
case kS390_I8x16AllTrue: {
SIMD_ALL_TRUE(0)
__ V128AnyTrue(i.OutputRegister(), i.InputSimd128Register(0),
kScratchReg);
break;
}
#undef SIMD_ALL_TRUE
// vector bitwise ops
case kS390_S128Const: {
uint64_t low = make_uint64(i.InputUint32(1), i.InputUint32(0));
......
src/wasm/baseline/s390/liftoff-assembler-s390.h
View file @ f572d69c
......@@ -2492,6 +2492,21 @@ SIMD_EXT_MUL_LIST(EMIT_SIMD_EXT_MUL)
#undef EMIT_SIMD_EXT_MUL
#undef SIMD_EXT_MUL_LIST
#define SIMD_ALL_TRUE_LIST(V) \
V(i64x2_alltrue, I64x2AllTrue) \
V(i32x4_alltrue, I32x4AllTrue) \
V(i16x8_alltrue, I16x8AllTrue) \
V(i8x16_alltrue, I8x16AllTrue)
#define EMIT_SIMD_ALL_TRUE(name, op) \
void LiftoffAssembler::emit_##name(LiftoffRegister dst, \
LiftoffRegister src) { \
op(dst.gp(), src.fp(), r0, kScratchDoubleReg); \
}
SIMD_ALL_TRUE_LIST(EMIT_SIMD_ALL_TRUE)
#undef EMIT_SIMD_ALL_TRUE
#undef SIMD_ALL_TRUE_LIST
void LiftoffAssembler::LoadTransform(LiftoffRegister dst, Register src_addr,
Register offset_reg, uintptr_t offset_imm,
LoadType type,
......@@ -2535,21 +2550,11 @@ void LiftoffAssembler::emit_f64x2_promote_low_f32x4(LiftoffRegister dst,
bailout(kSimd, "f64x2.promote_low_f32x4");
}
void LiftoffAssembler::emit_i64x2_alltrue(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "i64x2_alltrue");
}
void LiftoffAssembler::emit_i64x2_bitmask(LiftoffRegister dst,
LiftoffRegister src) {
I64x2BitMask(dst.gp(), src.fp(), r0, kScratchDoubleReg);
}
void LiftoffAssembler::emit_i32x4_alltrue(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "i32x4_alltrue");
}
void LiftoffAssembler::emit_i32x4_bitmask(LiftoffRegister dst,
LiftoffRegister src) {
I32x4BitMask(dst.gp(), src.fp(), r0, kScratchDoubleReg);
......@@ -2571,11 +2576,6 @@ void LiftoffAssembler::emit_i32x4_extadd_pairwise_i16x8_u(LiftoffRegister dst,
bailout(kSimd, "i32x4.extadd_pairwise_i16x8_u");
}
void LiftoffAssembler::emit_i16x8_alltrue(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "i16x8_alltrue");
}
void LiftoffAssembler::emit_i16x8_bitmask(LiftoffRegister dst,
LiftoffRegister src) {
I16x8BitMask(dst.gp(), src.fp(), r0, kScratchDoubleReg);
......@@ -2636,12 +2636,7 @@ void LiftoffAssembler::emit_i8x16_popcnt(LiftoffRegister dst,
void LiftoffAssembler::emit_v128_anytrue(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "v8x16_anytrue");
}
void LiftoffAssembler::emit_i8x16_alltrue(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "i8x16_alltrue");
V128AnyTrue(dst.gp(), src.fp(), r0);
}
void LiftoffAssembler::emit_i8x16_bitmask(LiftoffRegister dst,
......
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