Move architecture dependent files

Bug: v8:9247
Change-Id: I2f999ed3a8cc0931e5092f2ac6e709b8ff3f9e42
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1630678
Commit-Queue: Yang Guo <yangguo@chromium.org>
Reviewed-by: Ross McIlroy <rmcilroy@chromium.org>
Reviewed-by: Michael Starzinger <mstarzinger@chromium.org>
Cr-Commit-Position: refs/heads/master@{#61896}

OWNERS

@@ -22,5 +22,10 @@ per-file codereview.settings=file://INFRA_OWNERS
 per-file AUTHORS=file://COMMON_OWNERS
 per-file WATCHLIST=file://COMMON_OWNERS
 
+per-file *-mips*=file://MIPS_OWNERS
+per-file *-mips64*=file://MIPS_OWNERS
+per-file *-ppc*=file://PPC_OWNERS
+per-file *-s390*=file://S390_OWNERS
+
 # TEAM: v8-dev@googlegroups.com
 # COMPONENT: Blink>JavaScript

src/builtins/mips/builtins-mips.cc

@@ -13,9 +13,9 @@
 #include "src/logging/counters.h"
 // For interpreter_entry_return_pc_offset. TODO(jkummerow): Drop.
 #include "src/codegen/macro-assembler-inl.h"
+#include "src/codegen/mips/constants-mips.h"
 #include "src/codegen/register-configuration.h"
 #include "src/heap/heap-inl.h"
-#include "src/mips/constants-mips.h"
 #include "src/objects/cell.h"
 #include "src/objects/foreign.h"
 #include "src/objects/heap-number.h"

src/builtins/mips64/OWNERS

-xwafish@gmail.com

src/builtins/mips64/builtins-mips64.cc

@@ -13,9 +13,9 @@
 #include "src/logging/counters.h"
 // For interpreter_entry_return_pc_offset. TODO(jkummerow): Drop.
 #include "src/codegen/macro-assembler-inl.h"
+#include "src/codegen/mips64/constants-mips64.h"
 #include "src/codegen/register-configuration.h"
 #include "src/heap/heap-inl.h"
-#include "src/mips64/constants-mips64.h"
 #include "src/objects/cell.h"
 #include "src/objects/foreign.h"
 #include "src/objects/heap-number.h"

src/arm/assembler-arm-inl.h → src/codegen/arm/assembler-arm-inl.h

@@ -34,10 +34,10 @@
 // significantly by Google Inc.
 // Copyright 2012 the V8 project authors. All rights reserved.
 
-#ifndef V8_ARM_ASSEMBLER_ARM_INL_H_
-#define V8_ARM_ASSEMBLER_ARM_INL_H_
+#ifndef V8_CODEGEN_ARM_ASSEMBLER_ARM_INL_H_
+#define V8_CODEGEN_ARM_ASSEMBLER_ARM_INL_H_
 
-#include "src/arm/assembler-arm.h"
+#include "src/codegen/arm/assembler-arm.h"
 
 #include "src/codegen/assembler.h"
 #include "src/debug/debug.h"
@@ -55,7 +55,6 @@ int DoubleRegister::NumRegisters() {
   return CpuFeatures::IsSupported(VFP32DREGS) ? 32 : 16;
 }
 
-
 void RelocInfo::apply(intptr_t delta) {
   if (RelocInfo::IsInternalReference(rmode_)) {
     // absolute code pointer inside code object moves with the code object.
@@ -68,7 +67,6 @@ void RelocInfo::apply(intptr_t delta) {
   }
 }
 
-
 Address RelocInfo::target_address() {
   DCHECK(IsCodeTargetMode(rmode_) || IsRuntimeEntry(rmode_) ||
          IsWasmCall(rmode_));
@@ -88,16 +86,12 @@ Address RelocInfo::target_address_address() {
   }
 }
 
-
 Address RelocInfo::constant_pool_entry_address() {
   DCHECK(IsInConstantPool());
   return Assembler::constant_pool_entry_address(pc_, constant_pool_);
 }
 
-
-int RelocInfo::target_address_size() {
-  return kPointerSize;
-}
+int RelocInfo::target_address_size() { return kPointerSize; }
 
 HeapObject RelocInfo::target_object() {
   DCHECK(IsCodeTarget(rmode_) || rmode_ == FULL_EMBEDDED_OBJECT);
@@ -146,7 +140,6 @@ Address RelocInfo::target_internal_reference() {
   return Memory<Address>(pc_);
 }
 
-
 Address RelocInfo::target_internal_reference_address() {
   DCHECK(rmode_ == INTERNAL_REFERENCE);
   return pc_;
@@ -208,7 +201,6 @@ void Assembler::CheckBuffer() {
   MaybeCheckConstPool();
 }
 
-
 void Assembler::emit(Instr x) {
   CheckBuffer();
   *reinterpret_cast<Instr*>(pc_) = x;
@@ -230,12 +222,10 @@ void Assembler::deserialization_set_target_internal_reference_at(
   Memory<Address>(pc) = target;
 }
 
-
 bool Assembler::is_constant_pool_load(Address pc) {
   return IsLdrPcImmediateOffset(Memory<int32_t>(pc));
 }
 
-
 Address Assembler::constant_pool_entry_address(Address pc,
                                                Address constant_pool) {
   DCHECK(Assembler::IsLdrPcImmediateOffset(Memory<int32_t>(pc)));
@@ -243,7 +233,6 @@ Address Assembler::constant_pool_entry_address(Address pc,
   return pc + GetLdrRegisterImmediateOffset(instr) + Instruction::kPcLoadDelta;
 }
 
-
 Address Assembler::target_address_at(Address pc, Address constant_pool) {
   if (is_constant_pool_load(pc)) {
     // This is a constant pool lookup. Return the value in the constant pool.
@@ -369,4 +358,4 @@ T UseScratchRegisterScope::AcquireVfp() {
 }  // namespace internal
 }  // namespace v8
 
-#endif  // V8_ARM_ASSEMBLER_ARM_INL_H_
+#endif  // V8_CODEGEN_ARM_ASSEMBLER_ARM_INL_H_

src/arm/constants-arm.cc → src/codegen/arm/constants-arm.cc

@@ -4,8 +4,7 @@
 
 #if V8_TARGET_ARCH_ARM
 
-#include "src/arm/constants-arm.h"
-
+#include "src/codegen/arm/constants-arm.h"
 
 namespace v8 {
 namespace internal {
@@ -28,7 +27,6 @@ Float64 Instruction::DoubleImmedVmov() const {
   return Float64::FromBits(imm);
 }
 
-
 // These register names are defined in a way to match the native disassembler
 // formatting. See for example the command "objdump -d <binary file>".
 const char* Registers::names_[kNumRegisters] = {
@@ -36,7 +34,6 @@ const char* Registers::names_[kNumRegisters] = {
     "r8", "r9", "r10", "fp", "ip", "sp", "lr", "pc",
 };
 
-
 // List of alias names which can be used when referring to ARM registers.
 const Registers::RegisterAlias Registers::aliases_[] = {
     {10, "sl"},  {11, "r11"}, {12, "r12"},           {13, "r13"},
@@ -47,23 +44,18 @@ const Registers::RegisterAlias Registers::aliases_[] = {
 // These register names are defined in a way to match the native disassembler
 // formatting. See for example the command "objdump -d <binary file>".
 const char* VFPRegisters::names_[kNumVFPRegisters] = {
-    "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
-    "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
-    "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
-    "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
-    "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
-    "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
-    "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
-    "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31"
-};
-
+    "s0",  "s1",  "s2",  "s3",  "s4",  "s5",  "s6",  "s7",  "s8",  "s9",  "s10",
+    "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
+    "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", "d0",
+    "d1",  "d2",  "d3",  "d4",  "d5",  "d6",  "d7",  "d8",  "d9",  "d10", "d11",
+    "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", "d22",
+    "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31"};
 
 const char* VFPRegisters::Name(int reg, bool is_double) {
   DCHECK((0 <= reg) && (reg < kNumVFPRegisters));
   return names_[reg + (is_double ? kNumVFPSingleRegisters : 0)];
 }
 
-
 int VFPRegisters::Number(const char* name, bool* is_double) {
   for (int i = 0; i < kNumVFPRegisters; i++) {
     if (strcmp(names_[i], name) == 0) {
@@ -81,7 +73,6 @@ int VFPRegisters::Number(const char* name, bool* is_double) {
   return kNoRegister;
 }
 
-
 int Registers::Number(const char* name) {
   // Look through the canonical names.
   for (int i = 0; i < kNumRegisters; i++) {
@@ -103,7 +94,6 @@ int Registers::Number(const char* name) {
   return kNoRegister;
 }
 
-
 }  // namespace internal
 }  // namespace v8
 

src/arm/constants-arm.h → src/codegen/arm/constants-arm.h

@@ -2,8 +2,8 @@
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
-#ifndef V8_ARM_CONSTANTS_ARM_H_
-#define V8_ARM_CONSTANTS_ARM_H_
+#ifndef V8_CODEGEN_ARM_CONSTANTS_ARM_H_
+#define V8_CODEGEN_ARM_CONSTANTS_ARM_H_
 
 #include <stdint.h>
 
@@ -100,13 +100,11 @@ enum Condition {
   lo = cc   // C clear          Unsigned lower.
 };
 
-
 inline Condition NegateCondition(Condition cond) {
   DCHECK(cond != al);
   return static_cast<Condition>(cond ^ ne);
 }
 
-
 // -----------------------------------------------------------------------------
 // Instructions encoding.
 
@@ -137,7 +135,6 @@ enum Opcode {
   MVN = 15 << 21   // Move Not.
 };
 
-
 // The bits for bit 7-4 for some type 0 miscellaneous instructions.
 enum MiscInstructionsBits74 {
   // With bits 22-21 01.
@@ -150,7 +147,6 @@ enum MiscInstructionsBits74 {
   CLZ = 1 << 4
 };
 
-
 // Instruction encoding bits and masks.
 enum {
   H = 1 << 5,   // Halfword (or byte).
@@ -215,7 +211,6 @@ enum BarrierOption {
   SY = 0xf,
 };
 
-
 // -----------------------------------------------------------------------------
 // Addressing modes and instruction variants.
 
@@ -225,13 +220,8 @@ enum SBit {
   LeaveCC = 0 << 20  // Leave condition code unchanged.
 };
 
-
 // Status register selection.
-enum SRegister {
-  CPSR = 0 << 22,
-  SPSR = 1 << 22
-};
-
+enum SRegister { CPSR = 0 << 22, SPSR = 1 << 22 };
 
 // Shifter types for Data-processing operands as defined in section A5.1.2.
 enum ShiftOp {
@@ -248,7 +238,6 @@ enum ShiftOp {
   kNumberOfShifts = 4
 };
 
-
 // Status register fields.
 enum SRegisterField {
   CPSR_c = CPSR | 1 << 16,
@@ -267,37 +256,36 @@ using SRegisterFieldMask = uint32_t;
 // Memory operand addressing mode.
 enum AddrMode {
   // Bit encoding P U W.
-  Offset       = (8|4|0) << 21,  // Offset (without writeback to base).
-  PreIndex     = (8|4|1) << 21,  // Pre-indexed addressing with writeback.
-  PostIndex    = (0|4|0) << 21,  // Post-indexed addressing with writeback.
-  NegOffset    = (8|0|0) << 21,  // Negative offset (without writeback to base).
-  NegPreIndex  = (8|0|1) << 21,  // Negative pre-indexed with writeback.
-  NegPostIndex = (0|0|0) << 21   // Negative post-indexed with writeback.
+  Offset = (8 | 4 | 0) << 21,     // Offset (without writeback to base).
+  PreIndex = (8 | 4 | 1) << 21,   // Pre-indexed addressing with writeback.
+  PostIndex = (0 | 4 | 0) << 21,  // Post-indexed addressing with writeback.
+  NegOffset =
+      (8 | 0 | 0) << 21,  // Negative offset (without writeback to base).
+  NegPreIndex = (8 | 0 | 1) << 21,  // Negative pre-indexed with writeback.
+  NegPostIndex = (0 | 0 | 0) << 21  // Negative post-indexed with writeback.
 };
 
-
 // Load/store multiple addressing mode.
 enum BlockAddrMode {
   // Bit encoding P U W .
-  da           = (0|0|0) << 21,  // Decrement after.
-  ia           = (0|4|0) << 21,  // Increment after.
-  db           = (8|0|0) << 21,  // Decrement before.
-  ib           = (8|4|0) << 21,  // Increment before.
-  da_w         = (0|0|1) << 21,  // Decrement after with writeback to base.
-  ia_w         = (0|4|1) << 21,  // Increment after with writeback to base.
-  db_w         = (8|0|1) << 21,  // Decrement before with writeback to base.
-  ib_w         = (8|4|1) << 21,  // Increment before with writeback to base.
+  da = (0 | 0 | 0) << 21,    // Decrement after.
+  ia = (0 | 4 | 0) << 21,    // Increment after.
+  db = (8 | 0 | 0) << 21,    // Decrement before.
+  ib = (8 | 4 | 0) << 21,    // Increment before.
+  da_w = (0 | 0 | 1) << 21,  // Decrement after with writeback to base.
+  ia_w = (0 | 4 | 1) << 21,  // Increment after with writeback to base.
+  db_w = (8 | 0 | 1) << 21,  // Decrement before with writeback to base.
+  ib_w = (8 | 4 | 1) << 21,  // Increment before with writeback to base.
 
   // Alias modes for comparison when writeback does not matter.
-  da_x         = (0|0|0) << 21,  // Decrement after.
-  ia_x         = (0|4|0) << 21,  // Increment after.
-  db_x         = (8|0|0) << 21,  // Decrement before.
-  ib_x         = (8|4|0) << 21,  // Increment before.
+  da_x = (0 | 0 | 0) << 21,  // Decrement after.
+  ia_x = (0 | 4 | 0) << 21,  // Increment after.
+  db_x = (8 | 0 | 0) << 21,  // Decrement before.
+  ib_x = (8 | 4 | 0) << 21,  // Increment before.
 
-  kBlockAddrModeMask = (8|4|1) << 21
+  kBlockAddrModeMask = (8 | 4 | 1) << 21
 };
 
-
 // Coprocessor load/store operand size.
 enum LFlag {
   Long = 1 << 22,  // Long load/store coprocessor.
@@ -331,12 +319,7 @@ inline NeonSize NeonDataTypeToSize(NeonDataType dt) {
   return static_cast<NeonSize>(NeonSz(dt));
 }
 
-enum NeonListType {
-  nlt_1 = 0x7,
-  nlt_2 = 0xA,
-  nlt_3 = 0x6,
-  nlt_4 = 0x2
-};
+enum NeonListType { nlt_1 = 0x7, nlt_2 = 0xA, nlt_3 = 0x6, nlt_4 = 0x2 };
 
 // -----------------------------------------------------------------------------
 // Supervisor Call (svc) specific support.
@@ -357,7 +340,6 @@ const uint32_t kStopCodeMask = kStopCode - 1;
 const uint32_t kMaxStopCode = kStopCode - 1;
 const int32_t kDefaultStopCode = -1;
 
-
 // Type of VFP register. Determines register encoding.
 enum VFPRegPrecision {
   kSinglePrecision = 0,
@@ -366,10 +348,7 @@ enum VFPRegPrecision {
 };
 
 // VFP FPSCR constants.
-enum VFPConversionMode {
-  kFPSCRRounding = 0,
-  kDefaultRoundToZero = 1
-};
+enum VFPConversionMode { kFPSCRRounding = 0, kDefaultRoundToZero = 1 };
 
 // This mask does not include the "inexact" or "input denormal" cumulative
 // exceptions flags, because we usually don't want to check for it.
@@ -386,7 +365,6 @@ const uint32_t kVFPZConditionFlagBit = 1 << 30;
 const uint32_t kVFPCConditionFlagBit = 1 << 29;
 const uint32_t kVFPVConditionFlagBit = 1 << 28;
 
-
 // VFP rounding modes. See ARM DDI 0406B Page A2-29.
 enum VFPRoundingMode {
   RN = 0 << 22,  // Round to Nearest.
@@ -419,7 +397,6 @@ enum Hint { no_hint };
 // Hints are not used on the arm.  Negating is trivial.
 inline Hint NegateHint(Hint ignored) { return no_hint; }
 
-
 // -----------------------------------------------------------------------------
 // Instruction abstraction.
 
@@ -468,9 +445,7 @@ class Instruction {
 
   // Extract a single bit from the instruction bits and return it as bit 0 in
   // the result.
-  inline int Bit(int nr) const {
-    return (InstructionBits() >> nr) & 1;
-  }
+  inline int Bit(int nr) const { return (InstructionBits() >> nr) & 1; }
 
   // Extract a bit field <hi:lo> from the instruction bits and return it in the
   // least-significant bits of the result.
@@ -487,9 +462,7 @@ class Instruction {
 
   // Extract a single bit from the instruction bits and return it as bit 0 in
   // the result.
-  static inline int Bit(Instr instr, int nr) {
-    return (instr >> nr) & 1;
-  }
+  static inline int Bit(Instr instr, int nr) { return (instr >> nr) & 1; }
 
   // Extract a bit field <hi:lo> from the instruction bits and return it in the
   // least-significant bits of the result.
@@ -514,7 +487,6 @@ class Instruction {
   //   e.g. if instr is the 'addgt r0, r1, r2' instruction, encoded as
   //   0xC0810002 ConditionField(instr) will return 0xC.
 
-
   // Generally applicable fields
   inline int ConditionValue() const { return Bits(31, 28); }
   inline Condition ConditionField() const {
@@ -562,9 +534,7 @@ class Instruction {
   }
 
   // Fields used in Data processing instructions
-  inline int OpcodeValue() const {
-    return static_cast<Opcode>(Bits(24, 21));
-  }
+  inline int OpcodeValue() const { return static_cast<Opcode>(Bits(24, 21)); }
   inline Opcode OpcodeField() const {
     return static_cast<Opcode>(BitField(24, 21));
   }
@@ -586,7 +556,8 @@ class Instruction {
   DECLARE_STATIC_ACCESSOR(Immed8Value)
   inline int Immed4Value() const { return Bits(19, 16); }
   inline int ImmedMovwMovtValue() const {
-      return Immed4Value() << 12 | Offset12Value(); }
+    return Immed4Value() << 12 | Offset12Value();
+  }
   DECLARE_STATIC_ACCESSOR(ImmedMovwMovtValue)
 
   // Fields used in Load/Store instructions
@@ -638,10 +609,10 @@ class Instruction {
   inline bool IsSpecialType0() const { return (Bit(7) == 1) && (Bit(4) == 1); }
 
   // Test for miscellaneous instructions encodings of type 0 instructions.
-  inline bool IsMiscType0() const { return (Bit(24) == 1)
-                                           && (Bit(23) == 0)
-                                           && (Bit(20) == 0)
-                                           && ((Bit(7) == 0)); }
+  inline bool IsMiscType0() const {
+    return (Bit(24) == 1) && (Bit(23) == 0) && (Bit(20) == 0) &&
+           ((Bit(7) == 0));
+  }
 
   // Test for nop-like instructions which fall under type 1.
   inline bool IsNopLikeType1() const { return Bits(24, 8) == 0x120F0; }
@@ -672,7 +643,6 @@ class Instruction {
     return reinterpret_cast<Instruction*>(pc);
   }
 
-
  private:
   // Join split register codes, depending on register precision.
   // four_bit is the position of the least-significant bit of the four
@@ -696,7 +666,6 @@ class Instruction {
   DISALLOW_IMPLICIT_CONSTRUCTORS(Instruction);
 };
 
-
 // Helper functions for converting between register numbers and names.
 class Registers {
  public:
@@ -737,4 +706,4 @@ constexpr size_t kMaxPCRelativeCodeRangeInMB = 32;
 }  // namespace internal
 }  // namespace v8
 
-#endif  // V8_ARM_CONSTANTS_ARM_H_
+#endif  // V8_CODEGEN_ARM_CONSTANTS_ARM_H_

src/arm/cpu-arm.cc → src/codegen/arm/cpu-arm.cc

@@ -6,7 +6,7 @@
 #ifdef __arm__
 #ifdef __QNXNTO__
 #include <sys/mman.h>  // for cache flushing.
-#undef MAP_TYPE
+#undef MAP_TYPE        // NOLINT
 #else
 #include <sys/syscall.h>  // for cache flushing.
 #endif
@@ -56,7 +56,7 @@ V8_NOINLINE void CpuFeatures::FlushICache(void* start, size_t size) {
 
       "  pop {r7}\n"
       :
-    : "r" (beg), "r" (end), "r" (flg), [scno] "i" (__ARM_NR_cacheflush)
+      : "r"(beg), "r"(end), "r"(flg), [scno] "i"(__ARM_NR_cacheflush)
       : "memory");
 #endif
 #endif

src/arm/interface-descriptors-arm.cc → src/codegen/arm/interface-descriptors-arm.cc

@@ -74,7 +74,6 @@ const Register ApiGetterDescriptor::CallbackRegister() { return r3; }
 const Register GrowArrayElementsDescriptor::ObjectRegister() { return r0; }
 const Register GrowArrayElementsDescriptor::KeyRegister() { return r3; }
 
-
 // static
 const Register TypeConversionDescriptor::ArgumentRegister() { return r0; }
 

src/arm/macro-assembler-arm.cc → src/codegen/arm/macro-assembler-arm.cc

@@ -30,7 +30,7 @@
 // Satisfy cpplint check, but don't include platform-specific header. It is
 // included recursively via macro-assembler.h.
 #if 0
-#include "src/arm/macro-assembler-arm.h"
+#include "src/codegen/arm/macro-assembler-arm.h"
 #endif
 
 namespace v8 {
@@ -535,7 +535,6 @@ void MacroAssembler::Mls(Register dst, Register src1, Register src2,
   }
 }
 
-
 void MacroAssembler::And(Register dst, Register src1, const Operand& src2,
                          Condition cond) {
   if (!src2.IsRegister() && !src2.MustOutputRelocInfo(this) &&
@@ -553,7 +552,6 @@ void MacroAssembler::And(Register dst, Register src1, const Operand& src2,
   }
 }
 
-
 void MacroAssembler::Ubfx(Register dst, Register src1, int lsb, int width,
                           Condition cond) {
   DCHECK_LT(lsb, 32);
@@ -569,7 +567,6 @@ void MacroAssembler::Ubfx(Register dst, Register src1, int lsb, int width,
   }
 }
 
-
 void MacroAssembler::Sbfx(Register dst, Register src1, int lsb, int width,
                           Condition cond) {
   DCHECK_LT(lsb, 32);
@@ -590,7 +587,6 @@ void MacroAssembler::Sbfx(Register dst, Register src1, int lsb, int width,
   }
 }
 
-
 void TurboAssembler::Bfc(Register dst, Register src, int lsb, int width,
                          Condition cond) {
   DCHECK_LT(lsb, 32);
@@ -843,8 +839,9 @@ void TurboAssembler::PushCommonFrame(Register marker_reg) {
 
 void TurboAssembler::PushStandardFrame(Register function_reg) {
   DCHECK(!function_reg.is_valid() || function_reg.code() < cp.code());
-  stm(db_w, sp, (function_reg.is_valid() ? function_reg.bit() : 0) | cp.bit() |
-                    fp.bit() | lr.bit());
+  stm(db_w, sp,
+      (function_reg.is_valid() ? function_reg.bit() : 0) | cp.bit() | fp.bit() |
+          lr.bit());
   int offset = -StandardFrameConstants::kContextOffset;
   offset += function_reg.is_valid() ? kPointerSize : 0;
   add(fp, sp, Operand(offset));
@@ -1460,7 +1457,6 @@ void TurboAssembler::MovFromFloatResult(const DwVfpRegister dst) {
   }
 }
 
-
 // On ARM this is just a synonym to make the purpose clear.
 void TurboAssembler::MovFromFloatParameter(DwVfpRegister dst) {
   MovFromFloatResult(dst);
@@ -1744,7 +1740,6 @@ void MacroAssembler::PushStackHandler() {
   str(sp, MemOperand(r6));
 }
 
-
 void MacroAssembler::PopStackHandler() {
   UseScratchRegisterScope temps(this);
   Register scratch = temps.Acquire();
@@ -1756,11 +1751,8 @@ void MacroAssembler::PopStackHandler() {
   add(sp, sp, Operand(StackHandlerConstants::kSize - kPointerSize));
 }
 
-
-void MacroAssembler::CompareObjectType(Register object,
-                                       Register map,
-                                       Register type_reg,
-                                       InstanceType type) {
+void MacroAssembler::CompareObjectType(Register object, Register map,
+                                       Register type_reg, InstanceType type) {
   UseScratchRegisterScope temps(this);
   const Register temp = type_reg == no_reg ? temps.Acquire() : type_reg;
 
@@ -1768,9 +1760,7 @@ void MacroAssembler::CompareObjectType(Register object,
   CompareInstanceType(map, temp, type);
 }
 
-
-void MacroAssembler::CompareInstanceType(Register map,
-                                         Register type_reg,
+void MacroAssembler::CompareInstanceType(Register map, Register type_reg,
                                          InstanceType type) {
   ldrh(type_reg, FieldMemOperand(map, Map::kInstanceTypeOffset));
   cmp(type_reg, Operand(type));
@@ -1862,8 +1852,7 @@ void TurboAssembler::CallRuntimeWithCEntry(Runtime::FunctionId fid,
   CallCodeObject(centry);
 }
 
-void MacroAssembler::CallRuntime(const Runtime::Function* f,
-                                 int num_arguments,
+void MacroAssembler::CallRuntime(const Runtime::Function* f, int num_arguments,
                                  SaveFPRegsMode save_doubles) {
   // All parameters are on the stack.  r0 has the return value after call.
 
@@ -1932,7 +1921,6 @@ void MacroAssembler::IncrementCounter(StatsCounter* counter, int value,
   }
 }
 
-
 void MacroAssembler::DecrementCounter(StatsCounter* counter, int value,
                                       Register scratch1, Register scratch2) {
   DCHECK_GT(value, 0);
@@ -1945,8 +1933,7 @@ void MacroAssembler::DecrementCounter(StatsCounter* counter, int value,
 }
 
 void TurboAssembler::Assert(Condition cond, AbortReason reason) {
-  if (emit_debug_code())
-    Check(cond, reason);
+  if (emit_debug_code()) Check(cond, reason);
 }
 
 void TurboAssembler::AssertUnreachable(AbortReason reason) {
@@ -2011,7 +1998,6 @@ void MacroAssembler::LoadNativeContextSlot(int index, Register dst) {
   ldr(dst, ContextMemOperand(dst, index));
 }
 
-
 void TurboAssembler::InitializeRootRegister() {
   ExternalReference isolate_root = ExternalReference::isolate_root(isolate());
   mov(kRootRegister, Operand(isolate_root));
@@ -2057,7 +2043,6 @@ void MacroAssembler::AssertNotSmi(Register object) {
   }
 }
 
-
 void MacroAssembler::AssertSmi(Register object) {
   if (emit_debug_code()) {
     STATIC_ASSERT(kSmiTag == 0);
@@ -2092,7 +2077,6 @@ void MacroAssembler::AssertFunction(Register object) {
   }
 }
 
-
 void MacroAssembler::AssertBoundFunction(Register object) {
   if (emit_debug_code()) {
     STATIC_ASSERT(kSmiTag == 0);
@@ -2148,7 +2132,6 @@ void MacroAssembler::AssertUndefinedOrAllocationSite(Register object,
   }
 }
 
-
 void TurboAssembler::CheckFor32DRegs(Register scratch) {
   Move(scratch, ExternalReference::cpu_features());
   ldr(scratch, MemOperand(scratch));
@@ -2338,8 +2321,8 @@ void TurboAssembler::PrepareCallCFunction(int num_reg_arguments,
                                           int num_double_arguments,
                                           Register scratch) {
   int frame_alignment = ActivationFrameAlignment();
-  int stack_passed_arguments = CalculateStackPassedWords(
-      num_reg_arguments, num_double_arguments);
+  int stack_passed_arguments =
+      CalculateStackPassedWords(num_reg_arguments, num_double_arguments);
   if (frame_alignment > kPointerSize) {
     UseScratchRegisterScope temps(this);
     if (!scratch.is_valid()) scratch = temps.Acquire();
@@ -2362,7 +2345,6 @@ void TurboAssembler::MovToFloatParameter(DwVfpRegister src) {
   }
 }
 
-
 // On ARM this is just a synonym to make the purpose clear.
 void TurboAssembler::MovToFloatResult(DwVfpRegister src) {
   MovToFloatParameter(src);
@@ -2457,8 +2439,8 @@ void TurboAssembler::CallCFunctionHelper(Register function,
     Pop(scratch1);
   }
 
-  int stack_passed_arguments = CalculateStackPassedWords(
-      num_reg_arguments, num_double_arguments);
+  int stack_passed_arguments =
+      CalculateStackPassedWords(num_reg_arguments, num_double_arguments);
   if (ActivationFrameAlignment() > kPointerSize) {
     ldr(sp, MemOperand(sp, stack_passed_arguments * kPointerSize));
   } else {
@@ -2477,11 +2459,8 @@ void TurboAssembler::CheckPageFlag(Register object, int mask, Condition cc,
   b(cc, condition_met);
 }
 
-Register GetRegisterThatIsNotOneOf(Register reg1,
-                                   Register reg2,
-                                   Register reg3,
-                                   Register reg4,
-                                   Register reg5,
+Register GetRegisterThatIsNotOneOf(Register reg1, Register reg2, Register reg3,
+                                   Register reg4, Register reg5,
                                    Register reg6) {
   RegList regs = 0;
   if (reg1.is_valid()) regs |= reg1.bit();

src/arm/macro-assembler-arm.h → src/codegen/arm/macro-assembler-arm.h

@@ -6,10 +6,10 @@
 #error This header must be included via macro-assembler.h
 #endif
 
-#ifndef V8_ARM_MACRO_ASSEMBLER_ARM_H_
-#define V8_ARM_MACRO_ASSEMBLER_ARM_H_
+#ifndef V8_CODEGEN_ARM_MACRO_ASSEMBLER_ARM_H_
+#define V8_CODEGEN_ARM_MACRO_ASSEMBLER_ARM_H_
 
-#include "src/arm/assembler-arm.h"
+#include "src/codegen/arm/assembler-arm.h"
 #include "src/codegen/bailout-reason.h"
 #include "src/common/globals.h"
 #include "src/objects/contexts.h"
@@ -29,9 +29,7 @@ enum RememberedSetAction { EMIT_REMEMBERED_SET, OMIT_REMEMBERED_SET };
 enum SmiCheck { INLINE_SMI_CHECK, OMIT_SMI_CHECK };
 enum LinkRegisterStatus { kLRHasNotBeenSaved, kLRHasBeenSaved };
 
-
-Register GetRegisterThatIsNotOneOf(Register reg1,
-                                   Register reg2 = no_reg,
+Register GetRegisterThatIsNotOneOf(Register reg1, Register reg2 = no_reg,
                                    Register reg3 = no_reg,
                                    Register reg4 = no_reg,
                                    Register reg5 = no_reg,
@@ -666,17 +664,13 @@ class V8_EXPORT_PRIVATE MacroAssembler : public TurboAssembler {
   // register unless the heap_object register is the same register as one of the
   // other registers.
   // Type_reg can be no_reg. In that case a scratch register is used.
-  void CompareObjectType(Register heap_object,
-                         Register map,
-                         Register type_reg,
+  void CompareObjectType(Register heap_object, Register map, Register type_reg,
                          InstanceType type);
 
   // Compare instance type in a map.  map contains a valid map object whose
   // object type should be compared with the given type.  This both
   // sets the flags and leaves the object type in the type_reg register.
-  void CompareInstanceType(Register map,
-                           Register type_reg,
-                           InstanceType type);
+  void CompareInstanceType(Register map, Register type_reg, InstanceType type);
 
   // Compare the object in a register to a value from the root list.
   // Acquires a scratch register.
@@ -709,8 +703,7 @@ class V8_EXPORT_PRIVATE MacroAssembler : public TurboAssembler {
   // Runtime calls
 
   // Call a runtime routine.
-  void CallRuntime(const Runtime::Function* f,
-                   int num_arguments,
+  void CallRuntime(const Runtime::Function* f, int num_arguments,
                    SaveFPRegsMode save_doubles = kDontSaveFPRegs);
 
   // Convenience function: Same as above, but takes the fid instead.
@@ -743,10 +736,10 @@ class V8_EXPORT_PRIVATE MacroAssembler : public TurboAssembler {
   // ---------------------------------------------------------------------------
   // StatsCounter support
 
-  void IncrementCounter(StatsCounter* counter, int value,
-                        Register scratch1, Register scratch2);
-  void DecrementCounter(StatsCounter* counter, int value,
-                        Register scratch1, Register scratch2);
+  void IncrementCounter(StatsCounter* counter, int value, Register scratch1,
+                        Register scratch2);
+  void DecrementCounter(StatsCounter* counter, int value, Register scratch1,
+                        Register scratch2);
 
   // ---------------------------------------------------------------------------
   // Smi utilities
@@ -781,12 +774,12 @@ class V8_EXPORT_PRIVATE MacroAssembler : public TurboAssembler {
   // via --debug-code.
   void AssertUndefinedOrAllocationSite(Register object, Register scratch);
 
-  template<typename Field>
+  template <typename Field>
   void DecodeField(Register dst, Register src) {
     Ubfx(dst, src, Field::kShift, Field::kSize);
   }
 
-  template<typename Field>
+  template <typename Field>
   void DecodeField(Register reg) {
     DecodeField<Field>(reg, reg);
   }
@@ -814,7 +807,6 @@ inline MemOperand ContextMemOperand(Register context, int index = 0) {
   return MemOperand(context, Context::SlotOffset(index));
 }
 
-
 inline MemOperand NativeContextMemOperand() {
   return ContextMemOperand(cp, Context::NATIVE_CONTEXT_INDEX);
 }
@@ -824,4 +816,4 @@ inline MemOperand NativeContextMemOperand() {
 }  // namespace internal
 }  // namespace v8
 
-#endif  // V8_ARM_MACRO_ASSEMBLER_ARM_H_
+#endif  // V8_CODEGEN_ARM_MACRO_ASSEMBLER_ARM_H_

src/arm/register-arm.h → src/codegen/arm/register-arm.h

@@ -2,8 +2,8 @@
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
-#ifndef V8_ARM_REGISTER_ARM_H_
-#define V8_ARM_REGISTER_ARM_H_
+#ifndef V8_CODEGEN_ARM_REGISTER_ARM_H_
+#define V8_CODEGEN_ARM_REGISTER_ARM_H_
 
 #include "src/codegen/register.h"
 #include "src/codegen/reglist.h"
@@ -366,4 +366,4 @@ constexpr Register kRootRegister = r10;  // Roots array pointer.
 }  // namespace internal
 }  // namespace v8
 
-#endif  // V8_ARM_REGISTER_ARM_H_
+#endif  // V8_CODEGEN_ARM_REGISTER_ARM_H_

src/arm64/interface-descriptors-arm64.cc → src/codegen/arm64/interface-descriptors-arm64.cc

@@ -74,7 +74,6 @@ const Register ApiGetterDescriptor::CallbackRegister() { return x3; }
 const Register GrowArrayElementsDescriptor::ObjectRegister() { return x0; }
 const Register GrowArrayElementsDescriptor::KeyRegister() { return x3; }
 
-
 // static
 const Register TypeConversionDescriptor::ArgumentRegister() { return x0; }
 

src/arm64/register-arm64.cc → src/codegen/arm64/register-arm64.cc

@@ -4,7 +4,7 @@
 
 #if V8_TARGET_ARCH_ARM64
 
-#include "src/arm64/register-arm64.h"
+#include "src/codegen/arm64/register-arm64.h"
 
 namespace v8 {
 namespace internal {