[wasm-simd] Implement F64{S,U}ConvertI64x2 for arm64

Bug: v8:9813
Change-Id: Iffa5613f0d4226a25519feab8c2246be8e462cc9
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1981073
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Cr-Commit-Position: refs/heads/master@{#65619}

src/compiler/backend/arm64/code-generator-arm64.cc

@@ -1827,6 +1827,8 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ Mov(dst, i.InputInt8(1), i.InputSimd128Register(2).V2D(), 0);
       break;
     }
+      SIMD_UNOP_CASE(kArm64F64x2SConvertI64x2, Scvtf, 2D);
+      SIMD_UNOP_CASE(kArm64F64x2UConvertI64x2, Ucvtf, 2D);
       SIMD_UNOP_CASE(kArm64F64x2Abs, Fabs, 2D);
       SIMD_UNOP_CASE(kArm64F64x2Neg, Fneg, 2D);
       SIMD_UNOP_CASE(kArm64F64x2Sqrt, Fsqrt, 2D);

src/compiler/backend/arm64/instruction-codes-arm64.h

@@ -171,6 +171,8 @@ namespace compiler {
   V(Arm64F64x2Splat)                        \
   V(Arm64F64x2ExtractLane)                  \
   V(Arm64F64x2ReplaceLane)                  \
+  V(Arm64F64x2SConvertI64x2)                \
+  V(Arm64F64x2UConvertI64x2)                \
   V(Arm64F64x2Abs)                          \
   V(Arm64F64x2Neg)                          \
   V(Arm64F64x2Sqrt)                         \

src/compiler/backend/arm64/instruction-scheduler-arm64.cc

@@ -141,6 +141,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kArm64F64x2Splat:
     case kArm64F64x2ExtractLane:
     case kArm64F64x2ReplaceLane:
+    case kArm64F64x2SConvertI64x2:
+    case kArm64F64x2UConvertI64x2:
     case kArm64F64x2Abs:
     case kArm64F64x2Neg:
     case kArm64F64x2Sqrt:

src/compiler/backend/arm64/instruction-selector-arm64.cc

@@ -3130,6 +3130,8 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(F64x2Abs, kArm64F64x2Abs)                             \
   V(F64x2Neg, kArm64F64x2Neg)                             \
   V(F64x2Sqrt, kArm64F64x2Sqrt)                           \
+  V(F64x2SConvertI64x2, kArm64F64x2SConvertI64x2)         \
+  V(F64x2UConvertI64x2, kArm64F64x2UConvertI64x2)         \
   V(F32x4SConvertI32x4, kArm64F32x4SConvertI32x4)         \
   V(F32x4UConvertI32x4, kArm64F32x4UConvertI32x4)         \
   V(F32x4Abs, kArm64F32x4Abs)                             \

src/compiler/backend/instruction-selector.cc

@@ -2628,13 +2628,13 @@ void InstructionSelector::VisitI64x2ReplaceLaneI32Pair(Node* node) {
 #endif  // !V8_TARGET_ARCH_IA32
 
 #if !V8_TARGET_ARCH_X64
+#if !V8_TARGET_ARCH_ARM64
 void InstructionSelector::VisitF64x2SConvertI64x2(Node* node) {
   UNIMPLEMENTED();
 }
 void InstructionSelector::VisitF64x2UConvertI64x2(Node* node) {
   UNIMPLEMENTED();
 }
-#if !V8_TARGET_ARCH_ARM64
 #if !V8_TARGET_ARCH_ARM
 void InstructionSelector::VisitLoadTransform(Node* node) { UNIMPLEMENTED(); }
 #endif  // !V8_TARGET_ARCH_ARM

test/cctest/wasm/test-run-wasm-simd.cc

@@ -1526,7 +1526,7 @@ WASM_SIMD_TEST_NO_LOWERING(F64x2Qfms) {
 #endif  // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64
 #endif  // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_IA32
 
-#if V8_TARGET_ARCH_X64
+#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64
 WASM_SIMD_TEST_NO_LOWERING(F64x2ConvertI64x2) {
   WasmRunner<int32_t, int64_t> r(execution_tier, lower_simd);
   // Create two output vectors to hold signed and unsigned results.
@@ -1552,7 +1552,7 @@ WASM_SIMD_TEST_NO_LOWERING(F64x2ConvertI64x2) {
     }
   }
 }
-#endif  // V8_TARGET_ARCH_X64
+#endif  // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64
 
 WASM_SIMD_TEST(I32x4Splat) {
   WasmRunner<int32_t, int32_t> r(execution_tier, lower_simd);