Commit ee718489 authored by bmeurer@chromium.org's avatar bmeurer@chromium.org

Drop unused rdtsc instruction.

We do not use rdtsc anywhere and we won't ever use that in the
future, as it is totally unusable with multicore and out of
order execution.

R=jkummerow@chromium.org

Review URL: https://codereview.chromium.org/23112016

git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@16268 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
parent a36bda5c
...@@ -356,8 +356,6 @@ DEFINE_bool(enable_sse4_1, true, ...@@ -356,8 +356,6 @@ DEFINE_bool(enable_sse4_1, true,
"enable use of SSE4.1 instructions if available") "enable use of SSE4.1 instructions if available")
DEFINE_bool(enable_cmov, true, DEFINE_bool(enable_cmov, true,
"enable use of CMOV instruction if available") "enable use of CMOV instruction if available")
DEFINE_bool(enable_rdtsc, true,
"enable use of RDTSC instruction if available")
DEFINE_bool(enable_sahf, true, DEFINE_bool(enable_sahf, true,
"enable use of SAHF instruction if available (X64 only)") "enable use of SAHF instruction if available (X64 only)")
DEFINE_bool(enable_vfp3, ENABLE_VFP3_DEFAULT, DEFINE_bool(enable_vfp3, ENABLE_VFP3_DEFAULT,
......
...@@ -1310,14 +1310,6 @@ void Assembler::nop() { ...@@ -1310,14 +1310,6 @@ void Assembler::nop() {
} }
void Assembler::rdtsc() {
ASSERT(IsEnabled(RDTSC));
EnsureSpace ensure_space(this);
EMIT(0x0F);
EMIT(0x31);
}
void Assembler::ret(int imm16) { void Assembler::ret(int imm16) {
EnsureSpace ensure_space(this); EnsureSpace ensure_space(this);
ASSERT(is_uint16(imm16)); ASSERT(is_uint16(imm16));
......
...@@ -537,7 +537,6 @@ class CpuFeatures : public AllStatic { ...@@ -537,7 +537,6 @@ class CpuFeatures : public AllStatic {
if (f == SSE3 && !FLAG_enable_sse3) return false; if (f == SSE3 && !FLAG_enable_sse3) return false;
if (f == SSE4_1 && !FLAG_enable_sse4_1) return false; if (f == SSE4_1 && !FLAG_enable_sse4_1) return false;
if (f == CMOV && !FLAG_enable_cmov) return false; if (f == CMOV && !FLAG_enable_cmov) return false;
if (f == RDTSC && !FLAG_enable_rdtsc) return false;
return (supported_ & (static_cast<uint64_t>(1) << f)) != 0; return (supported_ & (static_cast<uint64_t>(1) << f)) != 0;
} }
...@@ -870,7 +869,6 @@ class Assembler : public AssemblerBase { ...@@ -870,7 +869,6 @@ class Assembler : public AssemblerBase {
void hlt(); void hlt();
void int3(); void int3();
void nop(); void nop();
void rdtsc();
void ret(int imm16); void ret(int imm16);
// Label operations & relative jumps (PPUM Appendix D) // Label operations & relative jumps (PPUM Appendix D)
......
...@@ -862,7 +862,6 @@ static const char* F0Mnem(byte f0byte) { ...@@ -862,7 +862,6 @@ static const char* F0Mnem(byte f0byte) {
switch (f0byte) { switch (f0byte) {
case 0x18: return "prefetch"; case 0x18: return "prefetch";
case 0xA2: return "cpuid"; case 0xA2: return "cpuid";
case 0x31: return "rdtsc";
case 0xBE: return "movsx_b"; case 0xBE: return "movsx_b";
case 0xBF: return "movsx_w"; case 0xBF: return "movsx_w";
case 0xB6: return "movzx_b"; case 0xB6: return "movzx_b";
......
...@@ -83,7 +83,7 @@ uint64_t OS::CpuFeaturesImpliedByPlatform() { ...@@ -83,7 +83,7 @@ uint64_t OS::CpuFeaturesImpliedByPlatform() {
// Mac OS X requires all these to install so we can assume they are present. // Mac OS X requires all these to install so we can assume they are present.
// These constants are defined by the CPUid instructions. // These constants are defined by the CPUid instructions.
const uint64_t one = 1; const uint64_t one = 1;
return (one << SSE2) | (one << CMOV) | (one << RDTSC) | (one << CPUID); return (one << SSE2) | (one << CMOV) | (one << CPUID);
#else #else
return 0; // Nothing special about the other systems. return 0; // Nothing special about the other systems.
#endif #endif
......
...@@ -438,7 +438,6 @@ enum CpuFeature { SSE4_1 = 32 + 19, // x86 ...@@ -438,7 +438,6 @@ enum CpuFeature { SSE4_1 = 32 + 19, // x86
SSE3 = 32 + 0, // x86 SSE3 = 32 + 0, // x86
SSE2 = 26, // x86 SSE2 = 26, // x86
CMOV = 15, // x86 CMOV = 15, // x86
RDTSC = 4, // x86
CPUID = 10, // x86 CPUID = 10, // x86
VFP3 = 1, // ARM VFP3 = 1, // ARM
ARMv7 = 2, // ARM ARMv7 = 2, // ARM
......
...@@ -1919,13 +1919,6 @@ void Assembler::pushfq() { ...@@ -1919,13 +1919,6 @@ void Assembler::pushfq() {
} }
void Assembler::rdtsc() {
EnsureSpace ensure_space(this);
emit(0x0F);
emit(0x31);
}
void Assembler::ret(int imm16) { void Assembler::ret(int imm16) {
EnsureSpace ensure_space(this); EnsureSpace ensure_space(this);
ASSERT(is_uint16(imm16)); ASSERT(is_uint16(imm16));
......
...@@ -475,7 +475,6 @@ class CpuFeatures : public AllStatic { ...@@ -475,7 +475,6 @@ class CpuFeatures : public AllStatic {
if (f == SSE3 && !FLAG_enable_sse3) return false; if (f == SSE3 && !FLAG_enable_sse3) return false;
if (f == SSE4_1 && !FLAG_enable_sse4_1) return false; if (f == SSE4_1 && !FLAG_enable_sse4_1) return false;
if (f == CMOV && !FLAG_enable_cmov) return false; if (f == CMOV && !FLAG_enable_cmov) return false;
if (f == RDTSC && !FLAG_enable_rdtsc) return false;
if (f == SAHF && !FLAG_enable_sahf) return false; if (f == SAHF && !FLAG_enable_sahf) return false;
return (supported_ & (static_cast<uint64_t>(1) << f)) != 0; return (supported_ & (static_cast<uint64_t>(1) << f)) != 0;
} }
...@@ -1176,7 +1175,6 @@ class Assembler : public AssemblerBase { ...@@ -1176,7 +1175,6 @@ class Assembler : public AssemblerBase {
void hlt(); void hlt();
void int3(); void int3();
void nop(); void nop();
void rdtsc();
void ret(int imm16); void ret(int imm16);
void setcc(Condition cc, Register reg); void setcc(Condition cc, Register reg);
......
...@@ -1229,8 +1229,8 @@ int DisassemblerX64::TwoByteOpcodeInstruction(byte* data) { ...@@ -1229,8 +1229,8 @@ int DisassemblerX64::TwoByteOpcodeInstruction(byte* data) {
current += PrintRightXMMOperand(current); current += PrintRightXMMOperand(current);
AppendToBuffer(", %s", NameOfXMMRegister(regop)); AppendToBuffer(", %s", NameOfXMMRegister(regop));
} else if (opcode == 0xA2 || opcode == 0x31) { } else if (opcode == 0xA2) {
// RDTSC or CPUID // CPUID
AppendToBuffer("%s", mnemonic); AppendToBuffer("%s", mnemonic);
} else if ((opcode & 0xF0) == 0x40) { } else if ((opcode & 0xF0) == 0x40) {
...@@ -1294,8 +1294,6 @@ const char* DisassemblerX64::TwoByteMnemonic(byte opcode) { ...@@ -1294,8 +1294,6 @@ const char* DisassemblerX64::TwoByteMnemonic(byte opcode) {
return "nop"; return "nop";
case 0x2A: // F2/F3 prefix. case 0x2A: // F2/F3 prefix.
return "cvtsi2s"; return "cvtsi2s";
case 0x31:
return "rdtsc";
case 0x51: // F2 prefix. case 0x51: // F2 prefix.
return "sqrtsd"; return "sqrtsd";
case 0x58: // F2 prefix. case 0x58: // F2 prefix.
......
...@@ -104,11 +104,6 @@ TEST(DisasmIa320) { ...@@ -104,11 +104,6 @@ TEST(DisasmIa320) {
CpuFeatureScope fscope(&assm, CPUID); CpuFeatureScope fscope(&assm, CPUID);
__ cpuid(); __ cpuid();
} }
{
CHECK(CpuFeatures::IsSupported(RDTSC));
CpuFeatureScope fscope(&assm, RDTSC);
__ rdtsc();
}
__ movsx_b(edx, ecx); __ movsx_b(edx, ecx);
__ movsx_w(edx, ecx); __ movsx_w(edx, ecx);
__ movzx_b(edx, ecx); __ movzx_b(edx, ecx);
......
...@@ -95,11 +95,6 @@ TEST(DisasmX64) { ...@@ -95,11 +95,6 @@ TEST(DisasmX64) {
CpuFeatures::Scope fscope(CPUID); CpuFeatures::Scope fscope(CPUID);
__ cpuid(); __ cpuid();
} }
{
CHECK(CpuFeatures::IsSupported(RDTSC));
CpuFeatures::Scope fscope(RDTSC);
__ rdtsc();
}
__ movsxbq(rdx, Operand(rcx, 0)); __ movsxbq(rdx, Operand(rcx, 0));
__ movsxwq(rdx, Operand(rcx, 0)); __ movsxwq(rdx, Operand(rcx, 0));
__ movzxbl(rdx, Operand(rcx, 0)); __ movzxbl(rdx, Operand(rcx, 0));
......
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