[wasm-simd][ia32] Fix instruction input constraints

The codegen for q15 rounding mul and dot incorrectly assumes that the
second operand is always a register.

For dot, we change the codegen to accept an Operand.

For q15, we change the instruction-selector to always use register.

Bug: v8:10971,v8:10993
Change-Id: I30a421de47ba61693ca73e616bcbc27ab01ac7bc
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2626712Reviewed-by: Bill Budge <bbudge@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#72180}

src/compiler/backend/ia32/code-generator-ia32.cc

@@ -2917,7 +2917,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
     }
     case kIA32I32x4DotI16x8S: {
       __ Pmaddwd(i.OutputSimd128Register(), i.InputSimd128Register(0),
-                 i.InputSimd128Register(1));
+                 i.InputOperand(1));
       break;
     }
     case kIA32I16x8Splat: {

src/compiler/backend/ia32/instruction-selector-ia32.cc

@@ -2257,7 +2257,6 @@ void InstructionSelector::VisitWord32AtomicPairCompareExchange(Node* node) {
   V(I64x2Eq)                               \
   V(I32x4DotI16x8S)                        \
   V(I16x8RoundingAverageU)                 \
-  V(I16x8Q15MulRSatS)                      \
   V(I8x16RoundingAverageU)
 
 // These opcodes require all inputs to be registers because the codegen is
@@ -2274,7 +2273,8 @@ void InstructionSelector::VisitWord32AtomicPairCompareExchange(Node* node) {
   V(I16x8ExtMulLowI8x16S)  \
   V(I16x8ExtMulHighI8x16S) \
   V(I16x8ExtMulLowI8x16U)  \
-  V(I16x8ExtMulHighI8x16U)
+  V(I16x8ExtMulHighI8x16U) \
+  V(I16x8Q15MulRSatS)
 
 #define SIMD_UNOP_LIST(V)   \
   V(F32x4Abs)               \