Commit e90600df authored by Milad Fa's avatar Milad Fa Committed by V8 LUCI CQ

PPC: remove simd `nearest int` ops from codegen

On PPC we don't have the `ties to even` FP roundings enabled,
therefore their equivalent Simd op will never get emitted.

Once support is added, the flag needs to be set under
`SupportedMachineOperatorFlags` within the instruction selector.
Setting this flag affects both the scalar and Simd variants
of this op.

Change-Id: I7d486def103045d2dee7cb691927feb19c3e5ef4
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2996747Reviewed-by: 's avatarJunliang Yan <junyan@redhat.com>
Commit-Queue: Milad Fa <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/master@{#75528}
parent 9908d102
...@@ -3344,10 +3344,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -3344,10 +3344,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ xvrdpiz(i.OutputSimd128Register(), i.InputSimd128Register(0)); __ xvrdpiz(i.OutputSimd128Register(), i.InputSimd128Register(0));
break; break;
} }
case kPPC_F64x2NearestInt: {
__ xvrdpi(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kPPC_F32x4Ceil: { case kPPC_F32x4Ceil: {
__ xvrspip(i.OutputSimd128Register(), i.InputSimd128Register(0)); __ xvrspip(i.OutputSimd128Register(), i.InputSimd128Register(0));
break; break;
...@@ -3360,10 +3356,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction( ...@@ -3360,10 +3356,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
__ xvrspiz(i.OutputSimd128Register(), i.InputSimd128Register(0)); __ xvrspiz(i.OutputSimd128Register(), i.InputSimd128Register(0));
break; break;
} }
case kPPC_F32x4NearestInt: {
__ xvrspi(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kPPC_I64x2BitMask: { case kPPC_I64x2BitMask: {
__ mov(kScratchReg, __ mov(kScratchReg,
Operand(0x8080808080800040)); // Select 0 for the high bits. Operand(0x8080808080800040)); // Select 0 for the high bits.
......
...@@ -218,7 +218,6 @@ namespace compiler { ...@@ -218,7 +218,6 @@ namespace compiler {
V(PPC_F64x2Ceil) \ V(PPC_F64x2Ceil) \
V(PPC_F64x2Floor) \ V(PPC_F64x2Floor) \
V(PPC_F64x2Trunc) \ V(PPC_F64x2Trunc) \
V(PPC_F64x2NearestInt) \
V(PPC_F64x2Pmin) \ V(PPC_F64x2Pmin) \
V(PPC_F64x2Pmax) \ V(PPC_F64x2Pmax) \
V(PPC_F64x2ConvertLowI32x4S) \ V(PPC_F64x2ConvertLowI32x4S) \
...@@ -247,7 +246,6 @@ namespace compiler { ...@@ -247,7 +246,6 @@ namespace compiler {
V(PPC_F32x4Ceil) \ V(PPC_F32x4Ceil) \
V(PPC_F32x4Floor) \ V(PPC_F32x4Floor) \
V(PPC_F32x4Trunc) \ V(PPC_F32x4Trunc) \
V(PPC_F32x4NearestInt) \
V(PPC_F32x4Pmin) \ V(PPC_F32x4Pmin) \
V(PPC_F32x4Pmax) \ V(PPC_F32x4Pmax) \
V(PPC_F32x4Qfma) \ V(PPC_F32x4Qfma) \
......
...@@ -136,7 +136,6 @@ int InstructionScheduler::GetTargetInstructionFlags( ...@@ -136,7 +136,6 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kPPC_F64x2Ceil: case kPPC_F64x2Ceil:
case kPPC_F64x2Floor: case kPPC_F64x2Floor:
case kPPC_F64x2Trunc: case kPPC_F64x2Trunc:
case kPPC_F64x2NearestInt:
case kPPC_F64x2Pmin: case kPPC_F64x2Pmin:
case kPPC_F64x2Pmax: case kPPC_F64x2Pmax:
case kPPC_F64x2ConvertLowI32x4S: case kPPC_F64x2ConvertLowI32x4S:
...@@ -167,7 +166,6 @@ int InstructionScheduler::GetTargetInstructionFlags( ...@@ -167,7 +166,6 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kPPC_F32x4Ceil: case kPPC_F32x4Ceil:
case kPPC_F32x4Floor: case kPPC_F32x4Floor:
case kPPC_F32x4Trunc: case kPPC_F32x4Trunc:
case kPPC_F32x4NearestInt:
case kPPC_F32x4Pmin: case kPPC_F32x4Pmin:
case kPPC_F32x4Pmax: case kPPC_F32x4Pmax:
case kPPC_F32x4DemoteF64x2Zero: case kPPC_F32x4DemoteF64x2Zero:
......
...@@ -1465,14 +1465,6 @@ void InstructionSelector::VisitFloat64RoundTiesAway(Node* node) { ...@@ -1465,14 +1465,6 @@ void InstructionSelector::VisitFloat64RoundTiesAway(Node* node) {
VisitRR(this, kPPC_RoundDouble, node); VisitRR(this, kPPC_RoundDouble, node);
} }
void InstructionSelector::VisitFloat32RoundTiesEven(Node* node) {
UNREACHABLE();
}
void InstructionSelector::VisitFloat64RoundTiesEven(Node* node) {
UNREACHABLE();
}
void InstructionSelector::VisitFloat32Neg(Node* node) { void InstructionSelector::VisitFloat32Neg(Node* node) {
VisitRR(this, kPPC_NegDouble, node); VisitRR(this, kPPC_NegDouble, node);
} }
...@@ -2300,7 +2292,6 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) { ...@@ -2300,7 +2292,6 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(F64x2Ceil) \ V(F64x2Ceil) \
V(F64x2Floor) \ V(F64x2Floor) \
V(F64x2Trunc) \ V(F64x2Trunc) \
V(F64x2NearestInt) \
V(F64x2ConvertLowI32x4S) \ V(F64x2ConvertLowI32x4S) \
V(F64x2ConvertLowI32x4U) \ V(F64x2ConvertLowI32x4U) \
V(F64x2PromoteLowF32x4) \ V(F64x2PromoteLowF32x4) \
...@@ -2314,7 +2305,6 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) { ...@@ -2314,7 +2305,6 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(F32x4Ceil) \ V(F32x4Ceil) \
V(F32x4Floor) \ V(F32x4Floor) \
V(F32x4Trunc) \ V(F32x4Trunc) \
V(F32x4NearestInt) \
V(F32x4DemoteF64x2Zero) \ V(F32x4DemoteF64x2Zero) \
V(I64x2Abs) \ V(I64x2Abs) \
V(I64x2Neg) \ V(I64x2Neg) \
...@@ -2697,6 +2687,18 @@ void InstructionSelector::AddOutputToSelectContinuation(OperandGenerator* g, ...@@ -2697,6 +2687,18 @@ void InstructionSelector::AddOutputToSelectContinuation(OperandGenerator* g,
UNREACHABLE(); UNREACHABLE();
} }
void InstructionSelector::VisitFloat32RoundTiesEven(Node* node) {
UNREACHABLE();
}
void InstructionSelector::VisitFloat64RoundTiesEven(Node* node) {
UNREACHABLE();
}
void InstructionSelector::VisitF64x2NearestInt(Node* node) { UNREACHABLE(); }
void InstructionSelector::VisitF32x4NearestInt(Node* node) { UNREACHABLE(); }
// static // static
MachineOperatorBuilder::Flags MachineOperatorBuilder::Flags
InstructionSelector::SupportedMachineOperatorFlags() { InstructionSelector::SupportedMachineOperatorFlags() {
......
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