[wasm-simd] Force some shuffles to use register for src0 and src1

test-run-wasm-simd/RunWasm_S8x16MultiShuffleFuzz_turbofan was failing
reliably with --no-enable-avx. (Even though the shuffle sequences were
randomly generated, in practice we quite quickly hit a case where we
will get a segfault.)

For 32x4swizzle and 32x4 shuffle, they use pshufd, which can take an
operand, but needs to be 16-byte aligned, which they are not, current.
So force them to be registers for now. This is similar to what we do in
the x64 selection too.

Bug: v8:9198
Change-Id: If319ff276202d4be095714a6cb18dec0d0551efd
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2032202Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#66086}

src/compiler/backend/ia32/instruction-selector-ia32.cc

@@ -2700,7 +2700,10 @@ void InstructionSelector::VisitS8x16Shuffle(Node* node) {
         // pshufd takes a single imm8 shuffle mask.
         opcode = kIA32S32x4Swizzle;
         no_same_as_first = true;
-        src0_needs_reg = false;
+        // TODO(v8:9198): This doesn't strictly require a register, forcing the
+        // swizzles to always use registers until generation of incorrect memory
+        // operands can be fixed.
+        src0_needs_reg = true;
         imms[imm_count++] = shuffle_mask;
       }
     } else {
@@ -2713,7 +2716,11 @@ void InstructionSelector::VisitS8x16Shuffle(Node* node) {
       } else {
         opcode = kIA32S32x4Shuffle;
         no_same_as_first = true;
-        src0_needs_reg = false;
+        // TODO(v8:9198): src0 and src1 is used by pshufd in codegen, which
+        // requires memory to be 16-byte aligned, since we cannot guarantee that
+        // yet, force using a register here.
+        src0_needs_reg = true;
+        src1_needs_reg = true;
         imms[imm_count++] = shuffle_mask;
         int8_t blend_mask = PackBlend4(shuffle32x4);
         imms[imm_count++] = blend_mask;