Commit e80f34ee authored by Liu Yu's avatar Liu Yu Committed by Commit Bot

[mips][wasm-simd][liftoff] Implement i64x2.eq

Besides, move load/store lane out of post-mvp.

Port: 97a935ee

Port: 848137c4

Change-Id: I8d98ed9949ba76648deefb1779057b76dff1304a
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2654865Reviewed-by: 's avatarZhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Commit-Queue: Zhao Jiazhong <zhaojiazhong-hf@loongson.cn>
Auto-Submit: Liu yu <liuyu@loongson.cn>
Cr-Commit-Position: refs/heads/master@{#72385}
parent 8d3468a1
...@@ -481,6 +481,10 @@ void InstructionSelector::VisitProtectedStore(Node* node) { ...@@ -481,6 +481,10 @@ void InstructionSelector::VisitProtectedStore(Node* node) {
UNIMPLEMENTED(); UNIMPLEMENTED();
} }
void InstructionSelector::VisitLoadLane(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitStoreLane(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitWord32And(Node* node) { void InstructionSelector::VisitWord32And(Node* node) {
MipsOperandGenerator g(this); MipsOperandGenerator g(this);
Int32BinopMatcher m(node); Int32BinopMatcher m(node);
......
...@@ -1915,6 +1915,11 @@ void LiftoffAssembler::emit_f32x4_le(LiftoffRegister dst, LiftoffRegister lhs, ...@@ -1915,6 +1915,11 @@ void LiftoffAssembler::emit_f32x4_le(LiftoffRegister dst, LiftoffRegister lhs,
bailout(kSimd, "emit_f32x4_le"); bailout(kSimd, "emit_f32x4_le");
} }
void LiftoffAssembler::emit_i64x2_eq(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kSimd, "emit_i64x2_eq");
}
void LiftoffAssembler::emit_f64x2_eq(LiftoffRegister dst, LiftoffRegister lhs, void LiftoffAssembler::emit_f64x2_eq(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) { LiftoffRegister rhs) {
bailout(kSimd, "emit_f64x2_eq"); bailout(kSimd, "emit_f64x2_eq");
......
...@@ -1852,6 +1852,11 @@ void LiftoffAssembler::emit_f32x4_le(LiftoffRegister dst, LiftoffRegister lhs, ...@@ -1852,6 +1852,11 @@ void LiftoffAssembler::emit_f32x4_le(LiftoffRegister dst, LiftoffRegister lhs,
fcle_w(dst.fp().toW(), lhs.fp().toW(), rhs.fp().toW()); fcle_w(dst.fp().toW(), lhs.fp().toW(), rhs.fp().toW());
} }
void LiftoffAssembler::emit_i64x2_eq(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
ceq_d(dst.fp().toW(), lhs.fp().toW(), rhs.fp().toW());
}
void LiftoffAssembler::emit_f64x2_eq(LiftoffRegister dst, LiftoffRegister lhs, void LiftoffAssembler::emit_f64x2_eq(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) { LiftoffRegister rhs) {
fceq_d(dst.fp().toW(), lhs.fp().toW(), rhs.fp().toW()); fceq_d(dst.fp().toW(), lhs.fp().toW(), rhs.fp().toW());
......
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