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Commit e7351c5e authored by Milad Farazmand's avatar Milad Farazmand Committed by Commit Bot
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PPC: [wasm-simd] Implement simd conversion operations 

Change-Id: I0eb2046d4bbb4305873866e99053d520d5e402f6
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2295882Reviewed-by: 's avatarJunliang Yan <jyan@ca.ibm.com>
Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com>
Cr-Commit-Position: refs/heads/master@{#68829}
parent 53e295ba
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Showing with 74 additions and 43 deletions
src/codegen/ppc/constants-ppc.h
View file @ e7351c5e
......@@ -359,23 +359,33 @@ using Instr = uint32_t;
/* Decimal Floating Test Data Group Quad */ \
V(dtstdgq, DTSTDGQ, 0xFC0001C4)
#define PPC_XX2_OPCODE_A_FORM_LIST(V) \
/* VSX Vector Absolute Value Double-Precision */ \
V(xvabsdp, XVABSDP, 0xF0000764) \
/* VSX Vector Negate Double-Precision */ \
V(xvnegdp, XVNEGDP, 0xF00007E4) \
/* VSX Vector Square Root Double-Precision */ \
V(xvsqrtdp, XVSQRTDP, 0xF000032C) \
/* VSX Vector Absolute Value Single-Precision */ \
V(xvabssp, XVABSSP, 0xF0000664) \
/* VSX Vector Negate Single-Precision */ \
V(xvnegsp, XVNEGSP, 0xF00006E4) \
/* VSX Vector Reciprocal Estimate Single-Precision */ \
V(xvresp, XVRESP, 0xF0000268) \
/* VSX Vector Reciprocal Square Root Estimate Single-Precision */ \
V(xvrsqrtesp, XVRSQRTESP, 0xF0000228) \
/* VSX Vector Square Root Single-Precision */ \
V(xvsqrtsp, XVSQRTSP, 0xF000022C)
#define PPC_XX2_OPCODE_A_FORM_LIST(V) \
/* VSX Vector Absolute Value Double-Precision */ \
V(xvabsdp, XVABSDP, 0xF0000764) \
/* VSX Vector Negate Double-Precision */ \
V(xvnegdp, XVNEGDP, 0xF00007E4) \
/* VSX Vector Square Root Double-Precision */ \
V(xvsqrtdp, XVSQRTDP, 0xF000032C) \
/* VSX Vector Absolute Value Single-Precision */ \
V(xvabssp, XVABSSP, 0xF0000664) \
/* VSX Vector Negate Single-Precision */ \
V(xvnegsp, XVNEGSP, 0xF00006E4) \
/* VSX Vector Reciprocal Estimate Single-Precision */ \
V(xvresp, XVRESP, 0xF0000268) \
/* VSX Vector Reciprocal Square Root Estimate Single-Precision */ \
V(xvrsqrtesp, XVRSQRTESP, 0xF0000228) \
/* VSX Vector Square Root Single-Precision */ \
V(xvsqrtsp, XVSQRTSP, 0xF000022C) \
/* VSX Vector Convert Single-Precision to Signed Fixed-Point Word */ \
/* Saturate */ \
V(xvcvspsxws, XVCVSPSXWS, 0xF0000260) \
/* VSX Vector Convert Single-Precision to Unsigned Fixed-Point Word */ \
/* Saturate */ \
V(xvcvspuxws, XVCVSPUXWS, 0xF0000220) \
/* VSX Vector Convert Signed Fixed-Point Word to Single-Precision */ \
V(xvcvsxwsp, XVCVSXWSP, 0xF00002E0) \
/* VSX Vector Convert Unsigned Fixed-Point Word to Single-Precision */ \
V(xvcvuxwsp, XVCVUXWSP, 0xF00002A0)
#define PPC_XX2_OPCODE_UNUSED_LIST(V) \
/* VSX Scalar Square Root Double-Precision */ \
......@@ -466,23 +476,15 @@ using Instr = uint32_t;
/* VSX Vector Convert Single-Precision to Signed Fixed-Point Doubleword */ \
/* Saturate */ \
V(xvcvspsxds, XVCVSPSXDS, 0xF0000660) \
/* VSX Vector Convert Single-Precision to Signed Fixed-Point Word */ \
/* Saturate */ \
V(xvcvspsxws, XVCVSPSXWS, 0xF0000260) \
/* VSX Vector Convert Single-Precision to Unsigned Fixed-Point */ \
/* Doubleword Saturate */ \
V(xvcvspuxds, XVCVSPUXDS, 0xF0000620) \
/* VSX Vector Convert Single-Precision to Unsigned Fixed-Point Word */ \
/* Saturate */ \
V(xvcvspuxws, XVCVSPUXWS, 0xF0000220) \
/* VSX Vector Convert Signed Fixed-Point Doubleword to Double-Precision */ \
V(xvcvsxddp, XVCVSXDDP, 0xF00007E0) \
/* VSX Vector Convert Signed Fixed-Point Doubleword to Single-Precision */ \
V(xvcvsxdsp, XVCVSXDSP, 0xF00006E0) \
/* VSX Vector Convert Signed Fixed-Point Word to Double-Precision */ \
V(xvcvsxwdp, XVCVSXWDP, 0xF00003E0) \
/* VSX Vector Convert Signed Fixed-Point Word to Single-Precision */ \
V(xvcvsxwsp, XVCVSXWSP, 0xF00002E0) \
/* VSX Vector Convert Unsigned Fixed-Point Doubleword to Double- */ \
/* Precision */ \
V(xvcvuxddp, XVCVUXDDP, 0xF00007A0) \
......@@ -491,8 +493,6 @@ using Instr = uint32_t;
V(xvcvuxdsp, XVCVUXDSP, 0xF00006A0) \
/* VSX Vector Convert Unsigned Fixed-Point Word to Double-Precision */ \
V(xvcvuxwdp, XVCVUXWDP, 0xF00003A0) \
/* VSX Vector Convert Unsigned Fixed-Point Word to Single-Precision */ \
V(xvcvuxwsp, XVCVUXWSP, 0xF00002A0) \
/* VSX Vector Negative Absolute Value Double-Precision */ \
V(xvnabsdp, XVNABSDP, 0xF00007A4) \
/* VSX Vector Negative Absolute Value Single-Precision */ \
......
src/compiler/backend/ppc/code-generator-ppc.cc
View file @ e7351c5e
......@@ -3057,6 +3057,29 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
break;
}
#undef SIMD_ALL_TRUE
case kPPC_I32x4SConvertF32x4: {
Simd128Register src = i.InputSimd128Register(0);
// NaN to 0
__ vor(kScratchDoubleReg, src, src);
__ xvcmpeqsp(kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg);
__ vand(kScratchDoubleReg, src, kScratchDoubleReg);
__ xvcvspsxws(i.OutputSimd128Register(), kScratchDoubleReg);
break;
}
case kPPC_I32x4UConvertF32x4: {
__ xvcvspuxws(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kPPC_F32x4SConvertI32x4: {
__ xvcvsxwsp(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kPPC_F32x4UConvertI32x4: {
__ xvcvuxwsp(i.OutputSimd128Register(), i.InputSimd128Register(0));
break;
}
case kPPC_StoreCompressTagged: {
ASSEMBLE_STORE_INTEGER(StoreTaggedField, StoreTaggedFieldX);
break;
......
src/compiler/backend/ppc/instruction-codes-ppc.h
View file @ e7351c5e
......@@ -219,6 +219,8 @@ namespace compiler {
V(PPC_F32x4RecipApprox) \
V(PPC_F32x4RecipSqrtApprox) \
V(PPC_F32x4Sqrt) \
V(PPC_F32x4SConvertI32x4) \
V(PPC_F32x4UConvertI32x4) \
V(PPC_I64x2Splat) \
V(PPC_I64x2ExtractLane) \
V(PPC_I64x2ReplaceLane) \
......@@ -261,6 +263,8 @@ namespace compiler {
V(PPC_I32x4ShrU) \
V(PPC_I32x4Neg) \
V(PPC_I32x4Abs) \
V(PPC_I32x4SConvertF32x4) \
V(PPC_I32x4UConvertF32x4) \
V(PPC_I16x8Splat) \
V(PPC_I16x8ExtractLaneU) \
V(PPC_I16x8ExtractLaneS) \
......
src/compiler/backend/ppc/instruction-scheduler-ppc.cc
View file @ e7351c5e
......@@ -142,6 +142,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kPPC_F32x4RecipApprox:
case kPPC_F32x4RecipSqrtApprox:
case kPPC_F32x4Sqrt:
case kPPC_F32x4SConvertI32x4:
case kPPC_F32x4UConvertI32x4:
case kPPC_I64x2Splat:
case kPPC_I64x2ExtractLane:
case kPPC_I64x2ReplaceLane:
......@@ -184,6 +186,8 @@ int InstructionScheduler::GetTargetInstructionFlags(
case kPPC_I32x4ShrU:
case kPPC_I32x4Neg:
case kPPC_I32x4Abs:
case kPPC_I32x4SConvertF32x4:
case kPPC_I32x4UConvertF32x4:
case kPPC_I16x8Splat:
case kPPC_I16x8ExtractLaneU:
case kPPC_I16x8ExtractLaneS:
......
src/compiler/backend/ppc/instruction-selector-ppc.cc
View file @ e7351c5e
......@@ -2236,6 +2236,12 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
V(V16x8AllTrue) \
V(V8x16AllTrue)
#define SIMD_CONVERSION_LIST(V) \
V(I32x4SConvertF32x4) \
V(I32x4UConvertF32x4) \
V(F32x4SConvertI32x4) \
V(F32x4UConvertI32x4)
#define SIMD_VISIT_SPLAT(Type) \
void InstructionSelector::Visit##Type##Splat(Node* node) { \
PPCOperandGenerator g(this); \
......@@ -2316,6 +2322,16 @@ SIMD_SHIFT_LIST(SIMD_VISIT_SHIFT)
SIMD_BOOL_LIST(SIMD_VISIT_BOOL)
#undef SIMD_VISIT_BOOL
#undef SIMD_BOOL_LIST
#define SIMD_VISIT_CONVERSION(Opcode) \
void InstructionSelector::Visit##Opcode(Node* node) { \
PPCOperandGenerator g(this); \
Emit(kPPC_##Opcode, g.DefineAsRegister(node), \
g.UseRegister(node->InputAt(0))); \
}
SIMD_CONVERSION_LIST(SIMD_VISIT_CONVERSION)
#undef SIMD_VISIT_CONVERSION
#undef SIMD_CONVERSION_LIST
#undef SIMD_TYPES
void InstructionSelector::VisitS128Zero(Node* node) {
......@@ -2403,22 +2419,6 @@ void InstructionSelector::VisitF32x4Min(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF32x4Max(Node* node) { UNIMPLEMENTED(); }
void InstructionSelector::VisitF32x4SConvertI32x4(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitF32x4UConvertI32x4(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI32x4SConvertF32x4(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI32x4UConvertF32x4(Node* node) {
UNIMPLEMENTED();
}
void InstructionSelector::VisitI32x4SConvertI16x8Low(Node* node) {
UNIMPLEMENTED();
}
......
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