[wasm-simd] Implement v128.andnot for arm64

Bug: v8:10082
Change-Id: I68e540c5b68c62fd6d43075e5244a9794d6d3eda
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1980908
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Cr-Commit-Position: refs/heads/master@{#65739}

src/compiler/backend/arm64/code-generator-arm64.cc

@@ -2395,6 +2395,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
              i.InputSimd128Register(2).V16B());
       break;
     }
+      SIMD_BINOP_CASE(kArm64S128AndNot, Bic, 16B);
     case kArm64S32x4Shuffle: {
       Simd128Register dst = i.OutputSimd128Register().V4S(),
                       src0 = i.InputSimd128Register(0).V4S(),

src/compiler/backend/arm64/instruction-codes-arm64.h

@@ -322,6 +322,7 @@ namespace compiler {
   V(Arm64S128Xor)                           \
   V(Arm64S128Not)                           \
   V(Arm64S128Select)                        \
+  V(Arm64S128AndNot)                        \
   V(Arm64S32x4ZipLeft)                      \
   V(Arm64S32x4ZipRight)                     \
   V(Arm64S32x4UnzipLeft)                    \

src/compiler/backend/arm64/instruction-scheduler-arm64.cc

@@ -292,6 +292,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kArm64S128Xor:
     case kArm64S128Not:
     case kArm64S128Select:
+    case kArm64S128AndNot:
     case kArm64S32x4ZipLeft:
     case kArm64S32x4ZipRight:
     case kArm64S32x4UnzipLeft:

src/compiler/backend/arm64/instruction-selector-arm64.cc

@@ -3258,7 +3258,8 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(I8x16RoundingAverageU, kArm64I8x16RoundingAverageU) \
   V(S128And, kArm64S128And)                             \
   V(S128Or, kArm64S128Or)                               \
-  V(S128Xor, kArm64S128Xor)
+  V(S128Xor, kArm64S128Xor)                             \
+  V(S128AndNot, kArm64S128AndNot)
 
 void InstructionSelector::VisitS128Zero(Node* node) {
   Arm64OperandGenerator g(this);

src/compiler/backend/instruction-selector.cc

@@ -2624,7 +2624,6 @@ void InstructionSelector::VisitI64x2ReplaceLaneI32Pair(Node* node) {
 #endif  // !V8_TARGET_ARCH_IA32
 
 #if !V8_TARGET_ARCH_X64
-void InstructionSelector::VisitS128AndNot(Node* node) { UNIMPLEMENTED(); }
 #if !V8_TARGET_ARCH_ARM64
 void InstructionSelector::VisitF64x2SConvertI64x2(Node* node) {
   UNIMPLEMENTED();
@@ -2632,6 +2631,7 @@ void InstructionSelector::VisitF64x2SConvertI64x2(Node* node) {
 void InstructionSelector::VisitF64x2UConvertI64x2(Node* node) {
   UNIMPLEMENTED();
 }
+void InstructionSelector::VisitS128AndNot(Node* node) { UNIMPLEMENTED(); }
 #if !V8_TARGET_ARCH_ARM
 void InstructionSelector::VisitLoadTransform(Node* node) { UNIMPLEMENTED(); }
 #endif  // !V8_TARGET_ARCH_ARM

test/cctest/wasm/test-run-wasm-simd.cc

@@ -1912,12 +1912,12 @@ WASM_SIMD_TEST(S128Xor) {
   RunI32x4BinOpTest(execution_tier, lower_simd, kExprS128Xor, Xor);
 }
 
-#if V8_TARGET_ARCH_X64
+#if V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64
 // Bitwise operation, doesn't really matter what simd type we test it with.
 WASM_SIMD_TEST_NO_LOWERING(S128AndNot) {
   RunI32x4BinOpTest(execution_tier, lower_simd, kExprS128AndNot, AndNot);
 }
-#endif  // V8_TARGET_ARCH_X64
+#endif  // V8_TARGET_ARCH_X64 || V8_TARGET_ARCH_ARM64
 
 WASM_SIMD_TEST(I32x4Eq) {
   RunI32x4BinOpTest(execution_tier, lower_simd, kExprI32x4Eq, Equal);