[codegen] Change a few DCHECKs to V8_ASSUMEs

This might or might not give clang-tidy a hint that the reported case
(see issue) cannot happen. It might also generate slightly better code
by giving hints to the compiler.
Note that V8_ASSUME is actually a DCHECK in DEBUG builds, so we do not
loose any checks here.

Some DCHECKs were removed because they are redundant
(RegisterBase::code() assumes to be only called on valid registers).

R=jkummerow@chromium.org

Bug: chromium:1349619
Change-Id: I467e7917a87ec86dd692f0edeed6bb72e0393cc4
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3804667
Commit-Queue: Clemens Backes <clemensb@chromium.org>
Reviewed-by: Jakob Kummerow <jkummerow@chromium.org>
Cr-Commit-Position: refs/heads/main@{#82273}

src/codegen/arm/register-arm.h

@@ -123,7 +123,6 @@ class SwVfpRegister : public RegisterBase<SwVfpRegister, kSwVfpAfterLast> {
   }
   void split_code(int* vm, int* m) const { split_code(code(), vm, m); }
   VfpRegList ToVfpRegList() const {
-    DCHECK(is_valid());
     // Each bit in the list corresponds to a S register.
     return uint64_t{0x1} << code();
   }
@@ -163,7 +162,6 @@ class DwVfpRegister : public RegisterBase<DwVfpRegister, kDoubleAfterLast> {
   }
   void split_code(int* vm, int* m) const { split_code(code(), vm, m); }
   VfpRegList ToVfpRegList() const {
-    DCHECK(is_valid());
     // A D register overlaps two S registers.
     return uint64_t{0x3} << (code() * 2);
   }
@@ -191,7 +189,6 @@ class LowDwVfpRegister
     return SwVfpRegister::from_code(code() * 2 + 1);
   }
   VfpRegList ToVfpRegList() const {
-    DCHECK(is_valid());
     // A D register overlaps two S registers.
     return uint64_t{0x3} << (code() * 2);
   }
@@ -212,7 +209,7 @@ enum Simd128RegisterCode {
 class QwNeonRegister : public RegisterBase<QwNeonRegister, kSimd128AfterLast> {
  public:
   static void split_code(int reg_code, int* vm, int* m) {
-    DCHECK(from_code(reg_code).is_valid());
+    V8_ASSUME(reg_code >= 0 && reg_code < kNumRegisters);
     int encoded_code = reg_code << 1;
     *m = (encoded_code & 0x10) >> 4;
     *vm = encoded_code & 0x0F;
@@ -223,7 +220,6 @@ class QwNeonRegister : public RegisterBase<QwNeonRegister, kSimd128AfterLast> {
     return DwVfpRegister::from_code(code() * 2 + 1);
   }
   VfpRegList ToVfpRegList() const {
-    DCHECK(is_valid());
     // A Q register overlaps four S registers.
     return uint64_t{0xf} << (code() * 4);
   }

src/codegen/register-base.h

@@ -41,7 +41,9 @@ class RegisterBase {
   constexpr bool is_valid() const { return reg_code_ != kCode_no_reg; }
 
   constexpr int8_t code() const {
-    DCHECK(is_valid());
+    // Only assume that it's positive (not no_reg); arm64 uses
+    // kSPRegInternalCode which is > kNumRegisters.
+    V8_ASSUME(reg_code_ >= 0);
     return reg_code_;
   }
 

src/codegen/x64/register-x64.h

@@ -214,7 +214,7 @@ static_assert(sizeof(XMMRegister) <= sizeof(int),
 class YMMRegister : public XMMRegister {
  public:
   static constexpr YMMRegister from_code(int code) {
-    DCHECK(base::IsInRange(code, 0, XMMRegister::kNumRegisters - 1));
+    V8_ASSUME(code >= 0 && code < XMMRegister::kNumRegisters);
     return YMMRegister(code);
   }
 

src/wasm/baseline/liftoff-register.h

@@ -205,8 +205,8 @@ class LiftoffRegister {
   static LiftoffRegister ForPair(Register low, Register high) {
     DCHECK(kNeedI64RegPair);
     DCHECK_NE(low, high);
-    storage_t combined_code = low.code() | high.code() << kBitsPerGpRegCode |
-                              1 << (2 * kBitsPerGpRegCode);
+    storage_t combined_code = low.code() | (high.code() << kBitsPerGpRegCode) |
+                              (1 << (2 * kBitsPerGpRegCode));
     return LiftoffRegister(combined_code);
   }