PPC: [wasm-simd] Implement simd AnyTrue and AllTrue

Change-Id: Ic60a47a931c8c359dce27ea5c774592bed1d4762
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2287230
Commit-Queue: Junliang Yan <jyan@ca.ibm.com>
Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com>
Reviewed-by: Junliang Yan <jyan@ca.ibm.com>
Cr-Commit-Position: refs/heads/master@{#68743}

src/compiler/backend/ppc/code-generator-ppc.cc

@@ -3015,6 +3015,48 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ vsububm(i.OutputSimd128Register(), tempFPReg1, kScratchDoubleReg);
       break;
     }
+    case kPPC_V64x2AnyTrue:
+    case kPPC_V32x4AnyTrue:
+    case kPPC_V16x8AnyTrue:
+    case kPPC_V8x16AnyTrue: {
+      Simd128Register src = i.InputSimd128Register(0);
+      Register dst = i.OutputRegister();
+      constexpr int bit_number = 24;
+      __ li(r0, Operand(0));
+      __ li(ip, Operand(-1));
+      // Check if both lanes are 0, if so then return false.
+      __ vxor(kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg);
+      __ vcmpequd(kScratchDoubleReg, src, kScratchDoubleReg, SetRC);
+      __ isel(dst, r0, ip, bit_number);
+      break;
+    }
+#define SIMD_ALL_TRUE(opcode)                                       \
+  Simd128Register src = i.InputSimd128Register(0);                  \
+  Register dst = i.OutputRegister();                                \
+  constexpr int bit_number = 24;                                    \
+  __ li(r0, Operand(0));                                            \
+  __ li(ip, Operand(-1));                                           \
+  /* Check if all lanes > 0, if not then return false.*/            \
+  __ vxor(kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg); \
+  __ opcode(kScratchDoubleReg, src, kScratchDoubleReg, SetRC);      \
+  __ isel(dst, ip, r0, bit_number);
+    case kPPC_V64x2AllTrue: {
+      SIMD_ALL_TRUE(vcmpgtud)
+      break;
+    }
+    case kPPC_V32x4AllTrue: {
+      SIMD_ALL_TRUE(vcmpgtuw)
+      break;
+    }
+    case kPPC_V16x8AllTrue: {
+      SIMD_ALL_TRUE(vcmpgtuh)
+      break;
+    }
+    case kPPC_V8x16AllTrue: {
+      SIMD_ALL_TRUE(vcmpgtub)
+      break;
+    }
+#undef SIMD_ALL_TRUE
     case kPPC_StoreCompressTagged: {
       ASSEMBLE_STORE_INTEGER(StoreTaggedField, StoreTaggedFieldX);
       break;

src/compiler/backend/ppc/instruction-codes-ppc.h

@@ -306,6 +306,14 @@ namespace compiler {
   V(PPC_I8x16ShrU)                   \
   V(PPC_I8x16Neg)                    \
   V(PPC_I8x16Abs)                    \
+  V(PPC_V64x2AnyTrue)                \
+  V(PPC_V32x4AnyTrue)                \
+  V(PPC_V16x8AnyTrue)                \
+  V(PPC_V8x16AnyTrue)                \
+  V(PPC_V64x2AllTrue)                \
+  V(PPC_V32x4AllTrue)                \
+  V(PPC_V16x8AllTrue)                \
+  V(PPC_V8x16AllTrue)                \
   V(PPC_S128And)                     \
   V(PPC_S128Or)                      \
   V(PPC_S128Xor)                     \

src/compiler/backend/ppc/instruction-scheduler-ppc.cc

@@ -229,6 +229,14 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kPPC_I8x16ShrU:
     case kPPC_I8x16Neg:
     case kPPC_I8x16Abs:
+    case kPPC_V64x2AnyTrue:
+    case kPPC_V32x4AnyTrue:
+    case kPPC_V16x8AnyTrue:
+    case kPPC_V8x16AnyTrue:
+    case kPPC_V64x2AllTrue:
+    case kPPC_V32x4AllTrue:
+    case kPPC_V16x8AllTrue:
+    case kPPC_V8x16AllTrue:
     case kPPC_S128And:
     case kPPC_S128Or:
     case kPPC_S128Xor:

src/compiler/backend/ppc/instruction-selector-ppc.cc

@@ -2228,6 +2228,14 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(I8x16ShrS)             \
   V(I8x16ShrU)
 
+#define SIMD_BOOL_LIST(V) \
+  V(V32x4AnyTrue)         \
+  V(V16x8AnyTrue)         \
+  V(V8x16AnyTrue)         \
+  V(V32x4AllTrue)         \
+  V(V16x8AllTrue)         \
+  V(V8x16AllTrue)
+
 #define SIMD_VISIT_SPLAT(Type)                               \
   void InstructionSelector::Visit##Type##Splat(Node* node) { \
     PPCOperandGenerator g(this);                             \
@@ -2298,6 +2306,16 @@ SIMD_UNOP_LIST(SIMD_VISIT_UNOP)
 SIMD_SHIFT_LIST(SIMD_VISIT_SHIFT)
 #undef SIMD_VISIT_SHIFT
 #undef SIMD_SHIFT_LIST
+
+#define SIMD_VISIT_BOOL(Opcode)                         \
+  void InstructionSelector::Visit##Opcode(Node* node) { \
+    PPCOperandGenerator g(this);                        \
+    Emit(kPPC_##Opcode, g.DefineAsRegister(node),       \
+         g.UseUniqueRegister(node->InputAt(0)));        \
+  }
+SIMD_BOOL_LIST(SIMD_VISIT_BOOL)
+#undef SIMD_VISIT_BOOL
+#undef SIMD_BOOL_LIST
 #undef SIMD_TYPES
 
 void InstructionSelector::VisitS128Zero(Node* node) {
@@ -2446,18 +2464,6 @@ void InstructionSelector::VisitI8x16UConvertI16x8(Node* node) {
   UNIMPLEMENTED();
 }
 
-void InstructionSelector::VisitV32x4AnyTrue(Node* node) { UNIMPLEMENTED(); }
-
-void InstructionSelector::VisitV32x4AllTrue(Node* node) { UNIMPLEMENTED(); }
-
-void InstructionSelector::VisitV16x8AnyTrue(Node* node) { UNIMPLEMENTED(); }
-
-void InstructionSelector::VisitV16x8AllTrue(Node* node) { UNIMPLEMENTED(); }
-
-void InstructionSelector::VisitV8x16AnyTrue(Node* node) { UNIMPLEMENTED(); }
-
-void InstructionSelector::VisitV8x16AllTrue(Node* node) { UNIMPLEMENTED(); }
-
 void InstructionSelector::VisitS8x16Shuffle(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitS8x16Swizzle(Node* node) { UNIMPLEMENTED(); }