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Commit e301d71f authored by Georg Neis's avatar Georg Neis Committed by V8 LUCI CQ
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[compiler] Teach InstructionScheduler about protected memory accesses 

Because these instructions can trap, we don't want them to be reordered
as freely as unprotected accesses.

As part of this, make explicit which opcodes support a MemoryAccessMode.

Bug: v8:12018
Change-Id: I9db3053d7d62ffce6d3c95d62adce71ae40dae62
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3172770Reviewed-by: 's avatarClemens Backes <clemensb@chromium.org>
Commit-Queue: Georg Neis <neis@chromium.org>
Cr-Commit-Position: refs/heads/main@{#77031}
parent bb5fa039
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Showing with 1483 additions and 1430 deletions
src/compiler/backend/arm/instruction-codes-arm.h
View file @ e301d71f
......@@ -11,7 +11,12 @@ namespace compiler {
// ARM-specific opcodes that specify which assembly sequence to emit.
// Most opcodes specify a single instruction.
// Opcodes that support a MemoryAccessMode.
#define TARGET_ARCH_OPCODE_WITH_MEMORY_ACCESS_MODE_LIST(V) // None.
#define TARGET_ARCH_OPCODE_LIST(V) \
TARGET_ARCH_OPCODE_WITH_MEMORY_ACCESS_MODE_LIST(V) \
V(ArmAdd) \
V(ArmAnd) \
V(ArmBic) \
......
src/compiler/backend/arm64/instruction-codes-arm64.h
View file @ e301d71f
......@@ -11,7 +11,40 @@ namespace compiler {
// ARM64-specific opcodes that specify which assembly sequence to emit.
// Most opcodes specify a single instruction.
// Opcodes that support a MemoryAccessMode.
#define TARGET_ARCH_OPCODE_WITH_MEMORY_ACCESS_MODE_LIST(V) \
V(Arm64Ldr) \
V(Arm64Ldrb) \
V(Arm64LdrD) \
V(Arm64Ldrh) \
V(Arm64LdrQ) \
V(Arm64LdrS) \
V(Arm64Ldrsb) \
V(Arm64LdrsbW) \
V(Arm64Ldrsh) \
V(Arm64LdrshW) \
V(Arm64Ldrsw) \
V(Arm64LdrW) \
V(Arm64LoadLane) \
V(Arm64LoadSplat) \
V(Arm64S128Load16x4S) \
V(Arm64S128Load16x4U) \
V(Arm64S128Load32x2S) \
V(Arm64S128Load32x2U) \
V(Arm64S128Load8x8S) \
V(Arm64S128Load8x8U) \
V(Arm64StoreLane) \
V(Arm64Str) \
V(Arm64Strb) \
V(Arm64StrD) \
V(Arm64Strh) \
V(Arm64StrQ) \
V(Arm64StrS) \
V(Arm64StrW)
#define TARGET_ARCH_OPCODE_LIST(V) \
TARGET_ARCH_OPCODE_WITH_MEMORY_ACCESS_MODE_LIST(V) \
V(Arm64Add) \
V(Arm64Add32) \
V(Arm64And) \
......@@ -160,31 +193,12 @@ namespace compiler {
V(Arm64Float64InsertHighWord32) \
V(Arm64Float64MoveU64) \
V(Arm64U64MoveFloat64) \
V(Arm64LdrS) \
V(Arm64StrS) \
V(Arm64LdrD) \
V(Arm64StrD) \
V(Arm64LdrQ) \
V(Arm64StrQ) \
V(Arm64Ldrb) \
V(Arm64Ldrsb) \
V(Arm64LdrsbW) \
V(Arm64Strb) \
V(Arm64Ldrh) \
V(Arm64Ldrsh) \
V(Arm64LdrshW) \
V(Arm64Strh) \
V(Arm64Ldrsw) \
V(Arm64LdrW) \
V(Arm64StrW) \
V(Arm64Ldr) \
V(Arm64LdrDecompressTaggedSigned) \
V(Arm64LdrDecompressTaggedPointer) \
V(Arm64LdrDecompressAnyTagged) \
V(Arm64LdarDecompressTaggedSigned) \
V(Arm64LdarDecompressTaggedPointer) \
V(Arm64LdarDecompressAnyTagged) \
V(Arm64Str) \
V(Arm64StrCompressTagged) \
V(Arm64StlrCompressTagged) \
V(Arm64DmbIsh) \
......@@ -327,15 +341,6 @@ namespace compiler {
V(Arm64I32x4AllTrue) \
V(Arm64I16x8AllTrue) \
V(Arm64I8x16AllTrue) \
V(Arm64LoadSplat) \
V(Arm64LoadLane) \
V(Arm64StoreLane) \
V(Arm64S128Load8x8S) \
V(Arm64S128Load8x8U) \
V(Arm64S128Load16x4S) \
V(Arm64S128Load16x4U) \
V(Arm64S128Load32x2S) \
V(Arm64S128Load32x2U) \
V(Arm64Word64AtomicLoadUint64) \
V(Arm64Word64AtomicStoreWord64) \
V(Arm64Word64AtomicAddUint64) \
......
src/compiler/backend/ia32/instruction-codes-ia32.h
View file @ e301d71f
......@@ -11,7 +11,12 @@ namespace compiler {
// IA32-specific opcodes that specify which assembly sequence to emit.
// Most opcodes specify a single instruction.
// Opcodes that support a MemoryAccessMode.
#define TARGET_ARCH_OPCODE_WITH_MEMORY_ACCESS_MODE_LIST(V) // None.
#define TARGET_ARCH_OPCODE_LIST(V) \
TARGET_ARCH_OPCODE_WITH_MEMORY_ACCESS_MODE_LIST(V) \
V(IA32Add) \
V(IA32And) \
V(IA32Cmp) \
......
src/compiler/backend/instruction-codes.h
View file @ e301d71f
......@@ -296,23 +296,50 @@ static_assert(
"All addressing modes must fit in the 5-bit AddressingModeField.");
using FlagsModeField = base::BitField<FlagsMode, 14, 3>;
using FlagsConditionField = base::BitField<FlagsCondition, 17, 5>;
using DeoptImmedArgsCountField = base::BitField<int, 22, 2>;
using DeoptFrameStateOffsetField = base::BitField<int, 24, 8>;
using MiscField = base::BitField<int, 22, 10>;
// {MiscField} is used for a variety of things, depending on the opcode.
// TODO(turbofan): There should be an abstraction that ensures safe encoding and
// decoding. {HasMemoryAccessMode} and its uses are a small step in that
// direction.
// LaneSizeField and AccessModeField are helper types to encode/decode a lane
// size, an access mode, or both inside the overlapping MiscField.
using LaneSizeField = base::BitField<int, 22, 8>;
using AccessModeField = base::BitField<MemoryAccessMode, 30, 2>;
// TODO(turbofan): {HasMemoryAccessMode} is currently only used to guard
// decoding (in CodeGenerator and InstructionScheduler). Encoding (in
// InstructionSelector) is not yet guarded. There are in fact instructions for
// which InstructionSelector does set a MemoryAccessMode but CodeGenerator
// doesn't care to consume it (e.g. kArm64LdrDecompressTaggedSigned). This is
// scary. {HasMemoryAccessMode} does not include these instructions, so they can
// be easily found by guarding encoding.
inline bool HasMemoryAccessMode(ArchOpcode opcode) {
switch (opcode) {
#define CASE(Name) \
case k##Name: \
return true;
TARGET_ARCH_OPCODE_WITH_MEMORY_ACCESS_MODE_LIST(CASE)
#undef CASE
default:
return false;
}
}
using DeoptImmedArgsCountField = base::BitField<int, 22, 2>;
using DeoptFrameStateOffsetField = base::BitField<int, 24, 8>;
// AtomicWidthField overlaps with MiscField and is used for the various Atomic
// opcodes. Only used on 64bit architectures. All atomic instructions on 32bit
// architectures are assumed to be 32bit wide.
using AtomicWidthField = base::BitField<AtomicWidth, 22, 2>;
// AtomicMemoryOrderField overlaps with MiscField and is used for the various
// Atomic opcodes. This field is not used on all architectures. It is used on
// architectures where the codegen for kSeqCst and kAcqRel differ only by
// emitting fences.
using AtomicMemoryOrderField = base::BitField<AtomicMemoryOrder, 24, 2>;
using AtomicStoreRecordWriteModeField = base::BitField<RecordWriteMode, 26, 4>;
using MiscField = base::BitField<int, 22, 10>;
// This static assertion serves as an early warning if we are about to exhaust
// the available opcode space. If we are about to exhaust it, we should start
......
src/compiler/backend/instruction-scheduler.cc
View file @ e301d71f
......@@ -167,7 +167,7 @@ void InstructionScheduler::AddInstruction(Instruction* instr) {
last_side_effect_instr_->AddSuccessor(new_node);
}
pending_loads_.push_back(new_node);
} else if (instr->IsDeoptimizeCall() || instr->IsTrap()) {
} else if (instr->IsDeoptimizeCall() || CanTrap(instr)) {
// Ensure that deopts or traps are not reordered with respect to
// side-effect instructions.
if (last_side_effect_instr_ != nullptr) {
......@@ -176,7 +176,7 @@ void InstructionScheduler::AddInstruction(Instruction* instr) {
}
// Update last deoptimization or trap point.
if (instr->IsDeoptimizeCall() || instr->IsTrap()) {
if (instr->IsDeoptimizeCall() || CanTrap(instr)) {
last_deopt_or_trap_ = new_node;
}
......
src/compiler/backend/instruction-scheduler.h
View file @ e301d71f
......@@ -169,6 +169,12 @@ class InstructionScheduler final : public ZoneObject {
return (GetInstructionFlags(instr) & kIsLoadOperation) != 0;
}
bool CanTrap(const Instruction* instr) const {
return instr->IsTrap() ||
(instr->HasMemoryAccessMode() &&
instr->memory_access_mode() == kMemoryAccessProtected);
}
// The scheduler will not move the following instructions before the last
// deopt/trap check:
// * loads (this is conservative)
......@@ -184,7 +190,7 @@ class InstructionScheduler final : public ZoneObject {
// trap point we encountered.
bool DependsOnDeoptOrTrap(const Instruction* instr) const {
return MayNeedDeoptOrTrapCheck(instr) || instr->IsDeoptimizeCall() ||
instr->IsTrap() || HasSideEffect(instr) || IsLoadOperation(instr);
CanTrap(instr) || HasSideEffect(instr) || IsLoadOperation(instr);
}
// Identify nops used as a definition point for live-in registers at
......
src/compiler/backend/instruction.h
View file @ e301d71f
......@@ -882,6 +882,13 @@ class V8_EXPORT_PRIVATE Instruction final {
return FlagsConditionField::decode(opcode());
}
int misc() const { return MiscField::decode(opcode()); }
bool HasMemoryAccessMode() const {
return compiler::HasMemoryAccessMode(arch_opcode());
}
MemoryAccessMode memory_access_mode() const {
DCHECK(HasMemoryAccessMode());
return AccessModeField::decode(opcode());
}
static Instruction* New(Zone* zone, InstructionCode opcode) {
return New(zone, opcode, 0, nullptr, 0, nullptr, 0, nullptr);
......
src/compiler/backend/x64/code-generator-x64.cc
View file @ e301d71f
......@@ -693,7 +693,7 @@ class WasmProtectedInstructionTrap final : public WasmOutOfLineTrap {
void EmitOOLTrapIfNeeded(Zone* zone, CodeGenerator* codegen,
InstructionCode opcode, Instruction* instr,
int pc) {
const MemoryAccessMode access_mode = AccessModeField::decode(opcode);
const MemoryAccessMode access_mode = instr->memory_access_mode();
if (access_mode == kMemoryAccessProtected) {
zone->New<WasmProtectedInstructionTrap>(codegen, pc, instr);
}
......@@ -703,7 +703,7 @@ void EmitOOLTrapIfNeeded(Zone* zone, CodeGenerator* codegen,
void EmitOOLTrapIfNeeded(Zone* zone, CodeGenerator* codegen,
InstructionCode opcode, Instruction* instr, int pc) {
DCHECK_NE(kMemoryAccessProtected, AccessModeField::decode(opcode));
DCHECK_NE(kMemoryAccessProtected, instr->memory_access_mode());
}
#endif // V8_ENABLE_WEBASSEMBLY
......
src/compiler/backend/x64/instruction-codes-x64.h
View file @ e301d71f
......@@ -11,7 +11,47 @@ namespace compiler {
// X64-specific opcodes that specify which assembly sequence to emit.
// Most opcodes specify a single instruction.
// Opcodes that support a MemoryAccessMode.
#define TARGET_ARCH_OPCODE_WITH_MEMORY_ACCESS_MODE_LIST(V) \
V(X64F64x2PromoteLowF32x4) \
V(X64Movb) \
V(X64Movdqu) \
V(X64Movl) \
V(X64Movq) \
V(X64Movsd) \
V(X64Movss) \
V(X64Movsxbl) \
V(X64Movsxbq) \
V(X64Movsxlq) \
V(X64Movsxwl) \
V(X64Movsxwq) \
V(X64Movw) \
V(X64Movzxbl) \
V(X64Movzxbq) \
V(X64Movzxwl) \
V(X64Movzxwq) \
V(X64Pextrb) \
V(X64Pextrw) \
V(X64Pinsrb) \
V(X64Pinsrd) \
V(X64Pinsrq) \
V(X64Pinsrw) \
V(X64S128Load16Splat) \
V(X64S128Load16x4S) \
V(X64S128Load16x4U) \
V(X64S128Load32Splat) \
V(X64S128Load32x2S) \
V(X64S128Load32x2U) \
V(X64S128Load64Splat) \
V(X64S128Load8Splat) \
V(X64S128Load8x8S) \
V(X64S128Load8x8U) \
V(X64S128Store32Lane) \
V(X64S128Store64Lane)
#define TARGET_ARCH_OPCODE_LIST(V) \
TARGET_ARCH_OPCODE_WITH_MEMORY_ACCESS_MODE_LIST(V) \
V(X64Add) \
V(X64Add32) \
V(X64And) \
......@@ -119,26 +159,10 @@ namespace compiler {
V(X64Float64Neg) \
V(X64Float32Abs) \
V(X64Float32Neg) \
V(X64Movsxbl) \
V(X64Movzxbl) \
V(X64Movsxbq) \
V(X64Movzxbq) \
V(X64Movb) \
V(X64Movsxwl) \
V(X64Movzxwl) \
V(X64Movsxwq) \
V(X64Movzxwq) \
V(X64Movw) \
V(X64Movl) \
V(X64Movsxlq) \
V(X64MovqDecompressTaggedSigned) \
V(X64MovqDecompressTaggedPointer) \
V(X64MovqDecompressAnyTagged) \
V(X64MovqCompressTagged) \
V(X64Movq) \
V(X64Movsd) \
V(X64Movss) \
V(X64Movdqu) \
V(X64BitcastFI) \
V(X64BitcastDL) \
V(X64BitcastIF) \
......@@ -173,7 +197,6 @@ namespace compiler {
V(X64F64x2Round) \
V(X64F64x2ConvertLowI32x4S) \
V(X64F64x2ConvertLowI32x4U) \
V(X64F64x2PromoteLowF32x4) \
V(X64F32x4Splat) \
V(X64F32x4ExtractLane) \
V(X64F32x4ReplaceLane) \
......@@ -300,12 +323,6 @@ namespace compiler {
V(X64I16x8Q15MulRSatS) \
V(X64I8x16Splat) \
V(X64I8x16ExtractLaneS) \
V(X64Pinsrb) \
V(X64Pinsrw) \
V(X64Pinsrd) \
V(X64Pinsrq) \
V(X64Pextrb) \
V(X64Pextrw) \
V(X64I8x16SConvertI16x8) \
V(X64I8x16Neg) \
V(X64I8x16Shl) \
......@@ -343,18 +360,6 @@ namespace compiler {
V(X64I8x16Swizzle) \
V(X64I8x16Shuffle) \
V(X64I8x16Popcnt) \
V(X64S128Load8Splat) \
V(X64S128Load16Splat) \
V(X64S128Load32Splat) \
V(X64S128Load64Splat) \
V(X64S128Load8x8S) \
V(X64S128Load8x8U) \
V(X64S128Load16x4S) \
V(X64S128Load16x4U) \
V(X64S128Load32x2S) \
V(X64S128Load32x2U) \
V(X64S128Store32Lane) \
V(X64S128Store64Lane) \
V(X64Shufps) \
V(X64S32x4Rotate) \
V(X64S32x4Swizzle) \
......
test/mjsunit/mjsunit.status
View file @ e301d71f
......@@ -1472,13 +1472,6 @@
'regress/regress-779407': [SKIP],
}], # variant == experimental_regexp
##############################################################################
['variant == instruction_scheduling or variant == stress_instruction_scheduling', {
# BUG(12018): These tests currently fail with --turbo-instruction-scheduling.
'regress/wasm/regress-1231950': [SKIP],
'regress/wasm/regress-1242300': [SKIP],
}], # variant == instruction_scheduling or variant == stress_instruction_scheduling
################################################################################
['single_generation', {
# These tests rely on allocation site tracking which only works in the young generation.
......
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