[ia32] Consolidate f32x4.splat and f64x2.splat instruction codes

Bug: v8:11217
Change-Id: I4a02af1b9b07470134ea893d532c545da63b26d3
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2568922
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Reviewed-by: Bill Budge <bbudge@chromium.org>
Cr-Commit-Position: refs/heads/master@{#71632}

src/compiler/backend/ia32/code-generator-ia32.cc

@@ -1914,16 +1914,16 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       }
       break;
     }
-    case kSSEF64x2Splat: {
-      DCHECK_EQ(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
-      XMMRegister dst = i.OutputSimd128Register();
-      __ shufpd(dst, dst, 0x0);
-      break;
-    }
-    case kAVXF64x2Splat: {
-      CpuFeatureScope avx_scope(tasm(), AVX);
+    case kIA32F64x2Splat: {
+      XMMRegister dst = i.OutputDoubleRegister();
       XMMRegister src = i.InputDoubleRegister(0);
-      __ vshufpd(i.OutputSimd128Register(), src, src, 0x0);
+      if (CpuFeatures::IsSupported(AVX)) {
+        CpuFeatureScope avx_scope(tasm(), AVX);
+        __ vshufpd(i.OutputSimd128Register(), src, src, 0x0);
+      } else {
+        DCHECK_EQ(dst, src);
+        __ shufpd(dst, src, 0x0);
+      }
       break;
     }
     case kSSEF64x2ExtractLane: {
@@ -2215,16 +2215,16 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       ASSEMBLE_SIMD_SIGN_SELECT(blendvpd);
       break;
     }
-    case kSSEF32x4Splat: {
-      DCHECK_EQ(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
-      XMMRegister dst = i.OutputSimd128Register();
-      __ shufps(dst, dst, 0x0);
-      break;
-    }
-    case kAVXF32x4Splat: {
-      CpuFeatureScope avx_scope(tasm(), AVX);
-      XMMRegister src = i.InputFloatRegister(0);
-      __ vshufps(i.OutputSimd128Register(), src, src, 0x0);
+    case kIA32F32x4Splat: {
+      XMMRegister dst = i.OutputDoubleRegister();
+      XMMRegister src = i.InputDoubleRegister(0);
+      if (CpuFeatures::IsSupported(AVX)) {
+        CpuFeatureScope avx_scope(tasm(), AVX);
+        __ vshufps(i.OutputSimd128Register(), src, src, 0x0);
+      } else {
+        DCHECK_EQ(dst, src);
+        __ shufps(dst, src, 0x0);
+      }
       break;
     }
     case kSSEF32x4ExtractLane: {

src/compiler/backend/ia32/instruction-codes-ia32.h

@@ -119,8 +119,7 @@ namespace compiler {
   V(IA32PushSimd128)               \
   V(IA32Poke)                      \
   V(IA32Peek)                      \
-  V(SSEF64x2Splat)                 \
-  V(AVXF64x2Splat)                 \
+  V(IA32F64x2Splat)                \
   V(SSEF64x2ExtractLane)           \
   V(AVXF64x2ExtractLane)           \
   V(SSEF64x2ReplaceLane)           \
@@ -151,8 +150,7 @@ namespace compiler {
   V(IA32I64x2BitMask)              \
   V(IA32I64x2Eq)                   \
   V(IA32I64x2SignSelect)           \
-  V(SSEF32x4Splat)                 \
-  V(AVXF32x4Splat)                 \
+  V(IA32F32x4Splat)                \
   V(SSEF32x4ExtractLane)           \
   V(AVXF32x4ExtractLane)           \
   V(IA32Insertps)                  \

src/compiler/backend/ia32/instruction-scheduler-ia32.cc

@@ -98,8 +98,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kAVXFloat32Neg:
     case kIA32BitcastFI:
     case kIA32BitcastIF:
-    case kSSEF64x2Splat:
-    case kAVXF64x2Splat:
+    case kIA32F64x2Splat:
     case kSSEF64x2ExtractLane:
     case kAVXF64x2ExtractLane:
     case kSSEF64x2ReplaceLane:
@@ -130,8 +129,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kIA32I64x2BitMask:
     case kIA32I64x2Eq:
     case kIA32I64x2SignSelect:
-    case kSSEF32x4Splat:
-    case kAVXF32x4Splat:
+    case kIA32F32x4Splat:
     case kSSEF32x4ExtractLane:
     case kAVXF32x4ExtractLane:
     case kIA32Insertps:

src/compiler/backend/ia32/instruction-selector-ia32.cc

@@ -2312,7 +2312,7 @@ void InstructionSelector::VisitF64x2Max(Node* node) {
 }
 
 void InstructionSelector::VisitF64x2Splat(Node* node) {
-  VisitRRSimd(this, node, kAVXF64x2Splat, kSSEF64x2Splat);
+  VisitRRSimd(this, node, kIA32F64x2Splat, kIA32F64x2Splat);
 }
 
 void InstructionSelector::VisitF64x2ExtractLane(Node* node) {
@@ -2379,7 +2379,7 @@ void InstructionSelector::VisitI64x2Mul(Node* node) {
 }
 
 void InstructionSelector::VisitF32x4Splat(Node* node) {
-  VisitRRSimd(this, node, kAVXF32x4Splat, kSSEF32x4Splat);
+  VisitRRSimd(this, node, kIA32F32x4Splat, kIA32F32x4Splat);
 }
 
 void InstructionSelector::VisitF32x4ExtractLane(Node* node) {