Commit e0f97ebb authored by joransiu's avatar joransiu Committed by Commit bot

S390: Fix fast-allocate to handle alignment

In fast-allocate, the path that leverages Add Mem-Imm fails to take
into account that the allocation size may be adjusted by kDoubleSize/2
for alignment.  Limit this instruction to 64-bit only.

Also guard PFDs with the proper facility check.
R=jyan@ca.ibm.com, michael_dawson@ca.ibm.com, bjaideep@ca.ibm.com
BUG=

Review-Url: https://codereview.chromium.org/2605063002
Cr-Commit-Position: refs/heads/master@{#41978}
parent 743b8976
...@@ -1625,10 +1625,12 @@ void MacroAssembler::Allocate(int object_size, Register result, ...@@ -1625,10 +1625,12 @@ void MacroAssembler::Allocate(int object_size, Register result,
StoreP(result_end, MemOperand(top_address)); StoreP(result_end, MemOperand(top_address));
} }
if (CpuFeatures::IsSupported(GENERAL_INSTR_EXT)) {
// Prefetch the allocation_top's next cache line in advance to // Prefetch the allocation_top's next cache line in advance to
// help alleviate potential cache misses. // help alleviate potential cache misses.
// Mode 2 - Prefetch the data into a cache line for store access. // Mode 2 - Prefetch the data into a cache line for store access.
pfd(r2, MemOperand(result, 256)); pfd(r2, MemOperand(result, 256));
}
// Tag object. // Tag object.
la(result, MemOperand(result, kHeapObjectTag)); la(result, MemOperand(result, kHeapObjectTag));
...@@ -1722,10 +1724,12 @@ void MacroAssembler::Allocate(Register object_size, Register result, ...@@ -1722,10 +1724,12 @@ void MacroAssembler::Allocate(Register object_size, Register result,
StoreP(result_end, MemOperand(top_address)); StoreP(result_end, MemOperand(top_address));
} }
if (CpuFeatures::IsSupported(GENERAL_INSTR_EXT)) {
// Prefetch the allocation_top's next cache line in advance to // Prefetch the allocation_top's next cache line in advance to
// help alleviate potential cache misses. // help alleviate potential cache misses.
// Mode 2 - Prefetch the data into a cache line for store access. // Mode 2 - Prefetch the data into a cache line for store access.
pfd(r2, MemOperand(result, 256)); pfd(r2, MemOperand(result, 256));
}
// Tag object. // Tag object.
la(result, MemOperand(result, kHeapObjectTag)); la(result, MemOperand(result, kHeapObjectTag));
...@@ -1780,10 +1784,12 @@ void MacroAssembler::FastAllocate(Register object_size, Register result, ...@@ -1780,10 +1784,12 @@ void MacroAssembler::FastAllocate(Register object_size, Register result,
} }
StoreP(result_end, MemOperand(top_address)); StoreP(result_end, MemOperand(top_address));
if (CpuFeatures::IsSupported(GENERAL_INSTR_EXT)) {
// Prefetch the allocation_top's next cache line in advance to // Prefetch the allocation_top's next cache line in advance to
// help alleviate potential cache misses. // help alleviate potential cache misses.
// Mode 2 - Prefetch the data into a cache line for store access. // Mode 2 - Prefetch the data into a cache line for store access.
pfd(r2, MemOperand(result, 256)); pfd(r2, MemOperand(result, 256));
}
// Tag object. // Tag object.
la(result, MemOperand(result, kHeapObjectTag)); la(result, MemOperand(result, kHeapObjectTag));
...@@ -1827,21 +1833,31 @@ void MacroAssembler::FastAllocate(int object_size, Register result, ...@@ -1827,21 +1833,31 @@ void MacroAssembler::FastAllocate(int object_size, Register result,
#endif #endif
} }
#if V8_TARGET_ARCH_S390X
// Limit to 64-bit only, as double alignment check above may adjust
// allocation top by an extra kDoubleSize/2.
if (CpuFeatures::IsSupported(GENERAL_INSTR_EXT) && is_int8(object_size)) { if (CpuFeatures::IsSupported(GENERAL_INSTR_EXT) && is_int8(object_size)) {
// Update allocation top. // Update allocation top.
AddP(MemOperand(top_address), Operand(object_size)); AddP(MemOperand(top_address), Operand(object_size));
} else { } else {
// Calculate new top using result. // Calculate new top using result.
AddP(result_end, result, Operand(object_size)); AddP(result_end, result, Operand(object_size));
// Update allocation top. // Update allocation top.
StoreP(result_end, MemOperand(top_address)); StoreP(result_end, MemOperand(top_address));
} }
#else
// Calculate new top using result.
AddP(result_end, result, Operand(object_size));
// Update allocation top.
StoreP(result_end, MemOperand(top_address));
#endif
if (CpuFeatures::IsSupported(GENERAL_INSTR_EXT)) {
// Prefetch the allocation_top's next cache line in advance to // Prefetch the allocation_top's next cache line in advance to
// help alleviate potential cache misses. // help alleviate potential cache misses.
// Mode 2 - Prefetch the data into a cache line for store access. // Mode 2 - Prefetch the data into a cache line for store access.
pfd(r2, MemOperand(result, 256)); pfd(r2, MemOperand(result, 256));
}
// Tag object. // Tag object.
la(result, MemOperand(result, kHeapObjectTag)); la(result, MemOperand(result, kHeapObjectTag));
......
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