[mips] Emit trampoline pool after Sdc1 instruction

Since there are some regression tests that use this instruction
many times in a row, trampoline pool can't be emitted. This commit
fixes this issue.

Change-Id: I7b575c4920f7e72a39051dee1ccca4baf9562ff1
Reviewed-on: https://chromium-review.googlesource.com/955696
Commit-Queue: Sreten Kovacevic <sreten.kovacevic@mips.com>
Reviewed-by: Ivica Bogosavljevic <ivica.bogosavljevic@mips.com>
Cr-Commit-Position: refs/heads/master@{#51846}

src/mips/macro-assembler-mips.cc

@@ -1167,6 +1167,7 @@ void TurboAssembler::Usdc1(FPURegister fd, const MemOperand& rs,
 void TurboAssembler::Ldc1(FPURegister fd, const MemOperand& src) {
   // Workaround for non-8-byte alignment of HeapNumber, convert 64-bit
   // load to two 32-bit loads.
+  {
     BlockTrampolinePoolScope block_trampoline_pool(this);
     DCHECK(Register::kMantissaOffset <= 4 && Register::kExponentOffset <= 4);
     MemOperand tmp = src;
@@ -1183,14 +1184,18 @@ void TurboAssembler::Ldc1(FPURegister fd, const MemOperand& src) {
       UseScratchRegisterScope temps(this);
       Register scratch = temps.Acquire();
       DCHECK(src.rm() != scratch);
-    lw(scratch, MemOperand(tmp.rm(), tmp.offset() + Register::kExponentOffset));
+      lw(scratch,
+         MemOperand(tmp.rm(), tmp.offset() + Register::kExponentOffset));
       Mthc1(scratch, fd);
     }
+  }
+  CheckTrampolinePoolQuick(1);
 }
 
 void TurboAssembler::Sdc1(FPURegister fd, const MemOperand& src) {
   // Workaround for non-8-byte alignment of HeapNumber, convert 64-bit
   // store to two 32-bit stores.
+  {
     BlockTrampolinePoolScope block_trampoline_pool(this);
     DCHECK(Register::kMantissaOffset <= 4 && Register::kExponentOffset <= 4);
     MemOperand tmp = src;
@@ -1208,6 +1213,8 @@ void TurboAssembler::Sdc1(FPURegister fd, const MemOperand& src) {
       Mfhc1(t8, fd);
       sw(t8, MemOperand(tmp.rm(), tmp.offset() + Register::kExponentOffset));
     }
+  }
+  CheckTrampolinePoolQuick(1);
 }
 
 void TurboAssembler::Ll(Register rd, const MemOperand& rs) {