C++20 fixes.

Math between disparate enums is deprecated.  Use constexprs instead.

This requires switching some caller code to work with the new non-enum
constants also.

Bug: chromium:1284275
Change-Id: Ifb3c8757ed62e2a0966120f830f0a7e282b53a16
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3661148
Auto-Submit: Peter Kasting <pkasting@chromium.org>
Commit-Queue: Leszek Swirski <leszeks@chromium.org>
Reviewed-by: Leszek Swirski <leszeks@chromium.org>
Reviewed-by: Deepti Gandluri <gdeepti@chromium.org>
Commit-Queue: Peter Kasting <pkasting@chromium.org>
Cr-Commit-Position: refs/heads/main@{#80722}

src/codegen/arm/assembler-arm.cc

@@ -4388,9 +4388,9 @@ enum IntegerBinOp {
   VQRDMULH
 };
 
-static Instr EncodeNeonBinOp(IntegerBinOp op, NeonDataType dt,
-                             QwNeonRegister dst, QwNeonRegister src1,
-                             QwNeonRegister src2) {
+static Instr EncodeNeonDataTypeBinOp(IntegerBinOp op, NeonDataType dt,
+                                     QwNeonRegister dst, QwNeonRegister src1,
+                                     QwNeonRegister src2) {
   int op_encoding = 0;
   switch (op) {
     case VADD:
@@ -4447,11 +4447,13 @@ static Instr EncodeNeonBinOp(IntegerBinOp op, NeonDataType dt,
          n * B7 | B6 | m * B5 | vm | op_encoding;
 }
 
-static Instr EncodeNeonBinOp(IntegerBinOp op, NeonSize size, QwNeonRegister dst,
-                             QwNeonRegister src1, QwNeonRegister src2) {
+static Instr EncodeNeonSizeBinOp(IntegerBinOp op, NeonSize size,
+                                 QwNeonRegister dst, QwNeonRegister src1,
+                                 QwNeonRegister src2) {
   // Map NeonSize values to the signed values in NeonDataType, so the U bit
   // will be 0.
-  return EncodeNeonBinOp(op, static_cast<NeonDataType>(size), dst, src1, src2);
+  return EncodeNeonDataTypeBinOp(op, static_cast<NeonDataType>(size), dst, src1,
+                                 src2);
 }
 
 void Assembler::vadd(QwNeonRegister dst, QwNeonRegister src1,
@@ -4467,7 +4469,7 @@ void Assembler::vadd(NeonSize size, QwNeonRegister dst, QwNeonRegister src1,
   DCHECK(IsEnabled(NEON));
   // Qd = vadd(Qn, Qm) SIMD integer addition.
   // Instruction details available in ARM DDI 0406C.b, A8-828.
-  emit(EncodeNeonBinOp(VADD, size, dst, src1, src2));
+  emit(EncodeNeonSizeBinOp(VADD, size, dst, src1, src2));
 }
 
 void Assembler::vqadd(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
@@ -4475,7 +4477,7 @@ void Assembler::vqadd(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
   DCHECK(IsEnabled(NEON));
   // Qd = vqadd(Qn, Qm) SIMD integer saturating addition.
   // Instruction details available in ARM DDI 0406C.b, A8-996.
-  emit(EncodeNeonBinOp(VQADD, dt, dst, src1, src2));
+  emit(EncodeNeonDataTypeBinOp(VQADD, dt, dst, src1, src2));
 }
 
 void Assembler::vsub(QwNeonRegister dst, QwNeonRegister src1,
@@ -4491,7 +4493,7 @@ void Assembler::vsub(NeonSize size, QwNeonRegister dst, QwNeonRegister src1,
   DCHECK(IsEnabled(NEON));
   // Qd = vsub(Qn, Qm) SIMD integer subtraction.
   // Instruction details available in ARM DDI 0406C.b, A8-1084.
-  emit(EncodeNeonBinOp(VSUB, size, dst, src1, src2));
+  emit(EncodeNeonSizeBinOp(VSUB, size, dst, src1, src2));
 }
 
 void Assembler::vqsub(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
@@ -4499,7 +4501,7 @@ void Assembler::vqsub(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
   DCHECK(IsEnabled(NEON));
   // Qd = vqsub(Qn, Qm) SIMD integer saturating subtraction.
   // Instruction details available in ARM DDI 0406C.b, A8-1020.
-  emit(EncodeNeonBinOp(VQSUB, dt, dst, src1, src2));
+  emit(EncodeNeonDataTypeBinOp(VQSUB, dt, dst, src1, src2));
 }
 
 void Assembler::vmlal(NeonDataType dt, QwNeonRegister dst, DwVfpRegister src1,
@@ -4534,7 +4536,7 @@ void Assembler::vmul(NeonSize size, QwNeonRegister dst, QwNeonRegister src1,
   DCHECK(IsEnabled(NEON));
   // Qd = vadd(Qn, Qm) SIMD integer multiply.
   // Instruction details available in ARM DDI 0406C.b, A8-960.
-  emit(EncodeNeonBinOp(VMUL, size, dst, src1, src2));
+  emit(EncodeNeonSizeBinOp(VMUL, size, dst, src1, src2));
 }
 
 void Assembler::vmull(NeonDataType dt, QwNeonRegister dst, DwVfpRegister src1,
@@ -4567,7 +4569,7 @@ void Assembler::vmin(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
   DCHECK(IsEnabled(NEON));
   // Qd = vmin(Qn, Qm) SIMD integer MIN.
   // Instruction details available in ARM DDI 0406C.b, A8-926.
-  emit(EncodeNeonBinOp(VMIN, dt, dst, src1, src2));
+  emit(EncodeNeonDataTypeBinOp(VMIN, dt, dst, src1, src2));
 }
 
 void Assembler::vmax(QwNeonRegister dst, QwNeonRegister src1,
@@ -4583,7 +4585,7 @@ void Assembler::vmax(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
   DCHECK(IsEnabled(NEON));
   // Qd = vmax(Qn, Qm) SIMD integer MAX.
   // Instruction details available in ARM DDI 0406C.b, A8-926.
-  emit(EncodeNeonBinOp(VMAX, dt, dst, src1, src2));
+  emit(EncodeNeonDataTypeBinOp(VMAX, dt, dst, src1, src2));
 }
 
 enum NeonShiftOp { VSHL, VSHR, VSLI, VSRI, VSRA };
@@ -4860,7 +4862,7 @@ void Assembler::vtst(NeonSize size, QwNeonRegister dst, QwNeonRegister src1,
   DCHECK(IsEnabled(NEON));
   // Qd = vtst(Qn, Qm) SIMD test integer operands.
   // Instruction details available in ARM DDI 0406C.b, A8-1098.
-  emit(EncodeNeonBinOp(VTST, size, dst, src1, src2));
+  emit(EncodeNeonSizeBinOp(VTST, size, dst, src1, src2));
 }
 
 void Assembler::vceq(QwNeonRegister dst, QwNeonRegister src1,
@@ -4876,7 +4878,7 @@ void Assembler::vceq(NeonSize size, QwNeonRegister dst, QwNeonRegister src1,
   DCHECK(IsEnabled(NEON));
   // Qd = vceq(Qn, Qm) SIMD integer compare equal.
   // Instruction details available in ARM DDI 0406C.b, A8-844.
-  emit(EncodeNeonBinOp(VCEQ, size, dst, src1, src2));
+  emit(EncodeNeonSizeBinOp(VCEQ, size, dst, src1, src2));
 }
 
 void Assembler::vceq(NeonSize size, QwNeonRegister dst, QwNeonRegister src1,
@@ -4901,7 +4903,7 @@ void Assembler::vcge(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
   DCHECK(IsEnabled(NEON));
   // Qd = vcge(Qn, Qm) SIMD integer compare greater or equal.
   // Instruction details available in ARM DDI 0406C.b, A8-848.
-  emit(EncodeNeonBinOp(VCGE, dt, dst, src1, src2));
+  emit(EncodeNeonDataTypeBinOp(VCGE, dt, dst, src1, src2));
 }
 
 void Assembler::vcgt(QwNeonRegister dst, QwNeonRegister src1,
@@ -4917,7 +4919,7 @@ void Assembler::vcgt(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
   DCHECK(IsEnabled(NEON));
   // Qd = vcgt(Qn, Qm) SIMD integer compare greater than.
   // Instruction details available in ARM DDI 0406C.b, A8-852.
-  emit(EncodeNeonBinOp(VCGT, dt, dst, src1, src2));
+  emit(EncodeNeonDataTypeBinOp(VCGT, dt, dst, src1, src2));
 }
 
 void Assembler::vclt(NeonSize size, QwNeonRegister dst, QwNeonRegister src,
@@ -4934,7 +4936,7 @@ void Assembler::vrhadd(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
   DCHECK(IsEnabled(NEON));
   // Qd = vrhadd(Qn, Qm) SIMD integer rounding halving add.
   // Instruction details available in ARM DDI 0406C.b, A8-1030.
-  emit(EncodeNeonBinOp(VRHADD, dt, dst, src1, src2));
+  emit(EncodeNeonDataTypeBinOp(VRHADD, dt, dst, src1, src2));
 }
 
 void Assembler::vext(QwNeonRegister dst, QwNeonRegister src1,
@@ -5044,7 +5046,7 @@ void Assembler::vqrdmulh(NeonDataType dt, QwNeonRegister dst,
                          QwNeonRegister src1, QwNeonRegister src2) {
   DCHECK(IsEnabled(NEON));
   DCHECK(dt == NeonS16 || dt == NeonS32);
-  emit(EncodeNeonBinOp(VQRDMULH, dt, dst, src1, src2));
+  emit(EncodeNeonDataTypeBinOp(VQRDMULH, dt, dst, src1, src2));
 }
 
 void Assembler::vcnt(QwNeonRegister dst, QwNeonRegister src) {

src/codegen/arm/macro-assembler-arm.cc

@@ -392,11 +392,6 @@ void TurboAssembler::Drop(Register count, Condition cond) {
   add(sp, sp, Operand(count, LSL, kPointerSizeLog2), LeaveCC, cond);
 }
 
-void TurboAssembler::Ret(int drop, Condition cond) {
-  Drop(drop, cond);
-  Ret(cond);
-}
-
 void MacroAssembler::TestCodeTIsMarkedForDeoptimization(Register codet,
                                                         Register scratch) {
   ldr(scratch, FieldMemOperand(codet, Code::kCodeDataContainerOffset));

src/codegen/arm/macro-assembler-arm.h

@@ -332,7 +332,6 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
   void Drop(Register count, Condition cond = al);
 
   void Ret(Condition cond = al);
-  void Ret(int drop, Condition cond = al);
 
   // Compare single values and move the result to the normal condition flags.
   void VFPCompareAndSetFlags(const SwVfpRegister src1, const SwVfpRegister src2,

src/compiler/backend/arm/code-generator-arm.cc

@@ -390,7 +390,7 @@ Condition FlagsConditionToCondition(FlagsCondition condition) {
     __ dmb(ISH);                                                       \
     __ bind(&binop);                                                   \
     __ ldrexd(r2, r3, i.TempRegister(0));                              \
-    __ instr1(i.TempRegister(1), r2, i.InputRegister(0), SBit::SetCC); \
+    __ instr1(i.TempRegister(1), r2, i.InputRegister(0), SetCC);       \
     __ instr2(i.TempRegister(2), r3, Operand(i.InputRegister(1)));     \
     DCHECK_EQ(LeaveCC, i.OutputSBit());                                \
     __ strexd(i.TempRegister(3), i.TempRegister(1), i.TempRegister(2), \
@@ -1224,7 +1224,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       // i.InputRegister(2) ... right low word.
       // i.InputRegister(3) ... right high word.
       __ add(i.OutputRegister(0), i.InputRegister(0), i.InputRegister(2),
-             SBit::SetCC);
+             SetCC);
       __ adc(i.OutputRegister(1), i.InputRegister(1),
              Operand(i.InputRegister(3)));
       DCHECK_EQ(LeaveCC, i.OutputSBit());
@@ -1235,7 +1235,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       // i.InputRegister(2) ... right low word.
       // i.InputRegister(3) ... right high word.
       __ sub(i.OutputRegister(0), i.InputRegister(0), i.InputRegister(2),
-             SBit::SetCC);
+             SetCC);
       __ sbc(i.OutputRegister(1), i.InputRegister(1),
              Operand(i.InputRegister(3)));
       DCHECK_EQ(LeaveCC, i.OutputSBit());
@@ -1520,7 +1520,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
         // Avoid INT32_MAX as an overflow indicator and use INT32_MIN instead,
         // because INT32_MIN allows easier out-of-bounds detection.
         __ cmn(i.OutputRegister(), Operand(1));
-        __ mov(i.OutputRegister(), Operand(INT32_MIN), SBit::LeaveCC, vs);
+        __ mov(i.OutputRegister(), Operand(INT32_MIN), LeaveCC, vs);
       }
       DCHECK_EQ(LeaveCC, i.OutputSBit());
       break;

src/wasm/baseline/arm/liftoff-assembler-arm.h

@@ -385,6 +385,9 @@ constexpr int MaskFromNeonDataType(NeonDataType dt) {
     case NeonS64:
     case NeonU64:
       return 63;
+    default:
+      UNREACHABLE();
+      return 0;
   }
 }
 

test/unittests/assembler/turbo-assembler-arm-unittest.cc

@@ -58,7 +58,7 @@ TEST_F(TurboAssemblerTest, TestCheck) {
   // Fail if the first parameter is 17.
   __ Move32BitImmediate(r1, Operand(17));
   __ cmp(r0, r1);  // 1st parameter is in {r0}.
-  __ Check(Condition::ne, AbortReason::kNoReason);
+  __ Check(ne, AbortReason::kNoReason);
   __ Ret();
 
   CodeDesc desc;