[wasm-simd][liftoff][x64] Add missing CPU features for instructions

These instructions require SSE4_1, we need to enable SSE4_1 before
calling them.

These will only fail when there is no AVX and no SSE4_2, and we
unfortunately is not a configuration we test (we test for no-AVX, and
no-AVX && no-SSE4_1 (which also means no-SSE4_2) && no-SSSE3 and
no-SSE3).

Change-Id: I3d49b9c68385c4b5b631c4a82e5e46d388500c06
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2513869Reviewed-by: Clemens Backes <clemensb@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#70910}

src/wasm/baseline/x64/liftoff-assembler-x64.h

@@ -2459,7 +2459,7 @@ void LiftoffAssembler::emit_i8x16_gt_u(LiftoffRegister dst, LiftoffRegister lhs,
     ref = kScratchDoubleReg;
   }
   liftoff::EmitSimdCommutativeBinOp<&Assembler::vpmaxub, &Assembler::pmaxub>(
-      this, dst, lhs, rhs);
+      this, dst, lhs, rhs, SSE4_1);
   Pcmpeqb(dst.fp(), ref);
   Pcmpeqb(kScratchDoubleReg, kScratchDoubleReg);
   Pxor(dst.fp(), kScratchDoubleReg);
@@ -2577,7 +2577,7 @@ void LiftoffAssembler::emit_i32x4_gt_u(LiftoffRegister dst, LiftoffRegister lhs,
     ref = kScratchDoubleReg;
   }
   liftoff::EmitSimdCommutativeBinOp<&Assembler::vpmaxud, &Assembler::pmaxud>(
-      this, dst, lhs, rhs);
+      this, dst, lhs, rhs, SSE4_1);
   Pcmpeqd(dst.fp(), ref);
   Pcmpeqd(kScratchDoubleReg, kScratchDoubleReg);
   Pxor(dst.fp(), kScratchDoubleReg);