[wasm-simd][x64] Implement i64x2.abs

Bug: v8:11416
Change-Id: I68bd6cade55472aed006638ea6d0c1d516d9d2cc
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2686308
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Reviewed-by: Bill Budge <bbudge@chromium.org>
Cr-Commit-Position: refs/heads/master@{#72666}

src/compiler/backend/instruction-selector.cc

@@ -2016,6 +2016,8 @@ void InstructionSelector::VisitNode(Node* node) {
       return MarkAsSimd128(node), VisitI64x2ReplaceLane(node);
     case IrOpcode::kI64x2ReplaceLaneI32Pair:
       return MarkAsSimd128(node), VisitI64x2ReplaceLaneI32Pair(node);
+    case IrOpcode::kI64x2Abs:
+      return MarkAsSimd128(node), VisitI64x2Abs(node);
     case IrOpcode::kI64x2Neg:
       return MarkAsSimd128(node), VisitI64x2Neg(node);
     case IrOpcode::kI64x2SConvertI32x4Low:
@@ -2804,6 +2806,11 @@ void InstructionSelector::VisitI64x2GtS(Node* node) { UNIMPLEMENTED(); }
 void InstructionSelector::VisitI64x2GeS(Node* node) { UNIMPLEMENTED(); }
 #endif  //! V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM64
 
+// TODO(v8:11416) Prototyping i64x2.abs.
+#if !V8_TARGET_ARCH_X64
+void InstructionSelector::VisitI64x2Abs(Node* node) { UNIMPLEMENTED(); }
+#endif  // !V8_TARGET_ARCH_X64
+
 void InstructionSelector::VisitFinishRegion(Node* node) { EmitIdentity(node); }
 
 void InstructionSelector::VisitParameter(Node* node) {

src/compiler/backend/x64/code-generator-x64.cc

@@ -2762,6 +2762,25 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ Pextrq(i.OutputRegister(), i.InputSimd128Register(0), i.InputInt8(1));
       break;
     }
+    case kX64I64x2Abs: {
+      XMMRegister dst = i.OutputSimd128Register();
+      XMMRegister src = i.InputSimd128Register(0);
+      if (CpuFeatures::IsSupported(AVX)) {
+        DCHECK_NE(dst, src);
+        CpuFeatureScope avx_scope(tasm(), AVX);
+        __ vpxor(dst, dst, dst);
+        __ vpsubq(dst, dst, src);
+        __ vblendvpd(dst, src, dst, src);
+      } else {
+        DCHECK_EQ(dst, src);
+        CpuFeatureScope sse_scope(tasm(), SSE3);
+        __ movshdup(kScratchDoubleReg, src);
+        __ psrad(kScratchDoubleReg, 31);
+        __ xorps(dst, kScratchDoubleReg);
+        __ psubq(dst, kScratchDoubleReg);
+      }
+      break;
+    }
     case kX64I64x2Neg: {
       XMMRegister dst = i.OutputSimd128Register();
       XMMRegister src = i.InputSimd128Register(0);

src/compiler/backend/x64/instruction-codes-x64.h

@@ -206,6 +206,7 @@ namespace compiler {
   V(X64F32x4DemoteF64x2Zero)              \
   V(X64I64x2Splat)                        \
   V(X64I64x2ExtractLane)                  \
+  V(X64I64x2Abs)                          \
   V(X64I64x2Neg)                          \
   V(X64I64x2BitMask)                      \
   V(X64I64x2Shl)                          \

src/compiler/backend/x64/instruction-scheduler-x64.cc

@@ -182,6 +182,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kX64F32x4DemoteF64x2Zero:
     case kX64I64x2Splat:
     case kX64I64x2ExtractLane:
+    case kX64I64x2Abs:
     case kX64I64x2Neg:
     case kX64I64x2BitMask:
     case kX64I64x2Shl:

src/compiler/backend/x64/instruction-selector-x64.cc

@@ -3805,6 +3805,17 @@ void InstructionSelector::VisitI64x2GeS(Node* node) {
   }
 }
 
+void InstructionSelector::VisitI64x2Abs(Node* node) {
+  X64OperandGenerator g(this);
+  if (CpuFeatures::IsSupported(AVX)) {
+    Emit(kX64I64x2Abs, g.DefineAsRegister(node),
+         g.UseUniqueRegister(node->InputAt(0)));
+  } else {
+    Emit(kX64I64x2Abs, g.DefineSameAsFirst(node),
+         g.UseRegister(node->InputAt(0)));
+  }
+}
+
 // static
 MachineOperatorBuilder::Flags
 InstructionSelector::SupportedMachineOperatorFlags() {

src/compiler/machine-operator.cc

@@ -426,6 +426,7 @@ std::ostream& operator<<(std::ostream& os, TruncateKind kind) {
   V(F32x4DemoteF64x2Zero, Operator::kNoProperties, 1, 0, 1)                \
   V(I64x2Splat, Operator::kNoProperties, 1, 0, 1)                          \
   V(I64x2SplatI32Pair, Operator::kNoProperties, 2, 0, 1)                   \
+  V(I64x2Abs, Operator::kNoProperties, 1, 0, 1)                            \
   V(I64x2Neg, Operator::kNoProperties, 1, 0, 1)                            \
   V(I64x2SConvertI32x4Low, Operator::kNoProperties, 1, 0, 1)               \
   V(I64x2SConvertI32x4High, Operator::kNoProperties, 1, 0, 1)              \

src/compiler/machine-operator.h

@@ -666,6 +666,7 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
   const Operator* I64x2ExtractLane(int32_t);
   const Operator* I64x2ReplaceLane(int32_t);
   const Operator* I64x2ReplaceLaneI32Pair(int32_t);
+  const Operator* I64x2Abs();
   const Operator* I64x2Neg();
   const Operator* I64x2SConvertI32x4Low();
   const Operator* I64x2SConvertI32x4High();

src/compiler/opcodes.h

@@ -823,6 +823,7 @@
   V(I64x2ExtractLane)           \
   V(I64x2ReplaceLane)           \
   V(I64x2ReplaceLaneI32Pair)    \
+  V(I64x2Abs)                   \
   V(I64x2Neg)                   \
   V(I64x2SConvertI32x4Low)      \
   V(I64x2SConvertI32x4High)     \

src/compiler/wasm-compiler.cc

@@ -4823,6 +4823,8 @@ Node* WasmGraphBuilder::SimdOp(wasm::WasmOpcode opcode, Node* const* inputs) {
                               inputs[0]);
     case wasm::kExprI64x2Splat:
       return graph()->NewNode(mcgraph()->machine()->I64x2Splat(), inputs[0]);
+    case wasm::kExprI64x2Abs:
+      return graph()->NewNode(mcgraph()->machine()->I64x2Abs(), inputs[0]);
     case wasm::kExprI64x2Neg:
       return graph()->NewNode(mcgraph()->machine()->I64x2Neg(), inputs[0]);
     case wasm::kExprI64x2SConvertI32x4Low:

test/cctest/wasm/test-run-wasm-simd.cc

@@ -951,13 +951,12 @@ WASM_SIMD_TEST(I64x2Neg) {
                    base::NegateWithWraparound);
 }
 
-WASM_SIMD_TEST(I64x2Abs) {
-  // TODO(v8:11416) Prototyping i64x2.abs.
-  if (TestExecutionTier::kInterpreter != execution_tier) {
-    return;
-  }
+// TODO(v8:11416) Prototyping i64x2.abs.
+#if V8_TARGET_ARCH_X64
+WASM_SIMD_TEST_NO_LOWERING(I64x2Abs) {
   RunI64x2UnOpTest(execution_tier, lower_simd, kExprI64x2Abs, std::abs);
 }
+#endif  // V8_TARGET_ARCH_X64
 
 void RunI64x2ShiftOpTest(TestExecutionTier execution_tier, LowerSimd lower_simd,
                          WasmOpcode opcode, Int64ShiftOp expected_op) {