Commit d6fcb81a authored by akos.palfi@imgtec.com's avatar akos.palfi@imgtec.com

MIPS: Use register parameters in ElementsTransitionGenerator.

Port r22384 (52caca20)

BUG=
R=mvstanton@chromium.org

Review URL: https://codereview.chromium.org/393693003

git-svn-id: https://v8.googlecode.com/svn/branches/bleeding_edge@22396 ce2b1a6d-e550-0410-aec6-3dcde31c8c00
parent 23887bf9
This diff is collapsed.
...@@ -927,10 +927,10 @@ static void KeyedStoreGenerateGenericHelper( ...@@ -927,10 +927,10 @@ static void KeyedStoreGenerateGenericHelper(
receiver_map, receiver_map,
t0, t0,
slow); slow);
ASSERT(receiver_map.is(a3)); // Transition code expects map in a3
AllocationSiteMode mode = AllocationSite::GetMode(FAST_SMI_ELEMENTS, AllocationSiteMode mode = AllocationSite::GetMode(FAST_SMI_ELEMENTS,
FAST_DOUBLE_ELEMENTS); FAST_DOUBLE_ELEMENTS);
ElementsTransitionGenerator::GenerateSmiToDouble(masm, mode, slow); ElementsTransitionGenerator::GenerateSmiToDouble(
masm, receiver, key, value, receiver_map, mode, slow);
__ lw(elements, FieldMemOperand(receiver, JSObject::kElementsOffset)); __ lw(elements, FieldMemOperand(receiver, JSObject::kElementsOffset));
__ jmp(&fast_double_without_map_check); __ jmp(&fast_double_without_map_check);
...@@ -941,10 +941,9 @@ static void KeyedStoreGenerateGenericHelper( ...@@ -941,10 +941,9 @@ static void KeyedStoreGenerateGenericHelper(
receiver_map, receiver_map,
t0, t0,
slow); slow);
ASSERT(receiver_map.is(a3)); // Transition code expects map in a3
mode = AllocationSite::GetMode(FAST_SMI_ELEMENTS, FAST_ELEMENTS); mode = AllocationSite::GetMode(FAST_SMI_ELEMENTS, FAST_ELEMENTS);
ElementsTransitionGenerator::GenerateMapChangeElementsTransition(masm, mode, ElementsTransitionGenerator::GenerateMapChangeElementsTransition(
slow); masm, receiver, key, value, receiver_map, mode, slow);
__ lw(elements, FieldMemOperand(receiver, JSObject::kElementsOffset)); __ lw(elements, FieldMemOperand(receiver, JSObject::kElementsOffset));
__ jmp(&finish_object_store); __ jmp(&finish_object_store);
...@@ -957,9 +956,9 @@ static void KeyedStoreGenerateGenericHelper( ...@@ -957,9 +956,9 @@ static void KeyedStoreGenerateGenericHelper(
receiver_map, receiver_map,
t0, t0,
slow); slow);
ASSERT(receiver_map.is(a3)); // Transition code expects map in a3
mode = AllocationSite::GetMode(FAST_DOUBLE_ELEMENTS, FAST_ELEMENTS); mode = AllocationSite::GetMode(FAST_DOUBLE_ELEMENTS, FAST_ELEMENTS);
ElementsTransitionGenerator::GenerateDoubleToObject(masm, mode, slow); ElementsTransitionGenerator::GenerateDoubleToObject(
masm, receiver, key, value, receiver_map, mode, slow);
__ lw(elements, FieldMemOperand(receiver, JSObject::kElementsOffset)); __ lw(elements, FieldMemOperand(receiver, JSObject::kElementsOffset));
__ jmp(&finish_object_store); __ jmp(&finish_object_store);
} }
......
...@@ -5674,14 +5674,30 @@ void MacroAssembler::JumpIfDictionaryInPrototypeChain( ...@@ -5674,14 +5674,30 @@ void MacroAssembler::JumpIfDictionaryInPrototypeChain(
} }
bool AreAliased(Register r1, Register r2, Register r3, Register r4) { bool AreAliased(Register reg1,
if (r1.is(r2)) return true; Register reg2,
if (r1.is(r3)) return true; Register reg3,
if (r1.is(r4)) return true; Register reg4,
if (r2.is(r3)) return true; Register reg5,
if (r2.is(r4)) return true; Register reg6,
if (r3.is(r4)) return true; Register reg7,
return false; Register reg8) {
int n_of_valid_regs = reg1.is_valid() + reg2.is_valid() +
reg3.is_valid() + reg4.is_valid() + reg5.is_valid() + reg6.is_valid() +
reg7.is_valid() + reg8.is_valid();
RegList regs = 0;
if (reg1.is_valid()) regs |= reg1.bit();
if (reg2.is_valid()) regs |= reg2.bit();
if (reg3.is_valid()) regs |= reg3.bit();
if (reg4.is_valid()) regs |= reg4.bit();
if (reg5.is_valid()) regs |= reg5.bit();
if (reg6.is_valid()) regs |= reg6.bit();
if (reg7.is_valid()) regs |= reg7.bit();
if (reg8.is_valid()) regs |= reg8.bit();
int n_of_non_aliasing_regs = NumRegs(regs);
return n_of_valid_regs != n_of_non_aliasing_regs;
} }
......
...@@ -84,7 +84,14 @@ Register GetRegisterThatIsNotOneOf(Register reg1, ...@@ -84,7 +84,14 @@ Register GetRegisterThatIsNotOneOf(Register reg1,
Register reg5 = no_reg, Register reg5 = no_reg,
Register reg6 = no_reg); Register reg6 = no_reg);
bool AreAliased(Register r1, Register r2, Register r3, Register r4); bool AreAliased(Register reg1,
Register reg2,
Register reg3 = no_reg,
Register reg4 = no_reg,
Register reg5 = no_reg,
Register reg6 = no_reg,
Register reg7 = no_reg,
Register reg8 = no_reg);
// ----------------------------------------------------------------------------- // -----------------------------------------------------------------------------
......
This diff is collapsed.
...@@ -938,10 +938,10 @@ static void KeyedStoreGenerateGenericHelper( ...@@ -938,10 +938,10 @@ static void KeyedStoreGenerateGenericHelper(
receiver_map, receiver_map,
a4, a4,
slow); slow);
ASSERT(receiver_map.is(a3)); // Transition code expects map in a3
AllocationSiteMode mode = AllocationSite::GetMode(FAST_SMI_ELEMENTS, AllocationSiteMode mode = AllocationSite::GetMode(FAST_SMI_ELEMENTS,
FAST_DOUBLE_ELEMENTS); FAST_DOUBLE_ELEMENTS);
ElementsTransitionGenerator::GenerateSmiToDouble(masm, mode, slow); ElementsTransitionGenerator::GenerateSmiToDouble(
masm, receiver, key, value, receiver_map, mode, slow);
__ ld(elements, FieldMemOperand(receiver, JSObject::kElementsOffset)); __ ld(elements, FieldMemOperand(receiver, JSObject::kElementsOffset));
__ jmp(&fast_double_without_map_check); __ jmp(&fast_double_without_map_check);
...@@ -952,10 +952,9 @@ static void KeyedStoreGenerateGenericHelper( ...@@ -952,10 +952,9 @@ static void KeyedStoreGenerateGenericHelper(
receiver_map, receiver_map,
a4, a4,
slow); slow);
ASSERT(receiver_map.is(a3)); // Transition code expects map in a3
mode = AllocationSite::GetMode(FAST_SMI_ELEMENTS, FAST_ELEMENTS); mode = AllocationSite::GetMode(FAST_SMI_ELEMENTS, FAST_ELEMENTS);
ElementsTransitionGenerator::GenerateMapChangeElementsTransition(masm, mode, ElementsTransitionGenerator::GenerateMapChangeElementsTransition(
slow); masm, receiver, key, value, receiver_map, mode, slow);
__ ld(elements, FieldMemOperand(receiver, JSObject::kElementsOffset)); __ ld(elements, FieldMemOperand(receiver, JSObject::kElementsOffset));
__ jmp(&finish_object_store); __ jmp(&finish_object_store);
...@@ -968,9 +967,9 @@ static void KeyedStoreGenerateGenericHelper( ...@@ -968,9 +967,9 @@ static void KeyedStoreGenerateGenericHelper(
receiver_map, receiver_map,
a4, a4,
slow); slow);
ASSERT(receiver_map.is(a3)); // Transition code expects map in a3
mode = AllocationSite::GetMode(FAST_DOUBLE_ELEMENTS, FAST_ELEMENTS); mode = AllocationSite::GetMode(FAST_DOUBLE_ELEMENTS, FAST_ELEMENTS);
ElementsTransitionGenerator::GenerateDoubleToObject(masm, mode, slow); ElementsTransitionGenerator::GenerateDoubleToObject(
masm, receiver, key, value, receiver_map, mode, slow);
__ ld(elements, FieldMemOperand(receiver, JSObject::kElementsOffset)); __ ld(elements, FieldMemOperand(receiver, JSObject::kElementsOffset));
__ jmp(&finish_object_store); __ jmp(&finish_object_store);
} }
......
...@@ -5862,14 +5862,30 @@ void MacroAssembler::JumpIfDictionaryInPrototypeChain( ...@@ -5862,14 +5862,30 @@ void MacroAssembler::JumpIfDictionaryInPrototypeChain(
} }
bool AreAliased(Register r1, Register r2, Register r3, Register r4) { bool AreAliased(Register reg1,
if (r1.is(r2)) return true; Register reg2,
if (r1.is(r3)) return true; Register reg3,
if (r1.is(r4)) return true; Register reg4,
if (r2.is(r3)) return true; Register reg5,
if (r2.is(r4)) return true; Register reg6,
if (r3.is(r4)) return true; Register reg7,
return false; Register reg8) {
int n_of_valid_regs = reg1.is_valid() + reg2.is_valid() +
reg3.is_valid() + reg4.is_valid() + reg5.is_valid() + reg6.is_valid() +
reg7.is_valid() + reg8.is_valid();
RegList regs = 0;
if (reg1.is_valid()) regs |= reg1.bit();
if (reg2.is_valid()) regs |= reg2.bit();
if (reg3.is_valid()) regs |= reg3.bit();
if (reg4.is_valid()) regs |= reg4.bit();
if (reg5.is_valid()) regs |= reg5.bit();
if (reg6.is_valid()) regs |= reg6.bit();
if (reg7.is_valid()) regs |= reg7.bit();
if (reg8.is_valid()) regs |= reg8.bit();
int n_of_non_aliasing_regs = NumRegs(regs);
return n_of_valid_regs != n_of_non_aliasing_regs;
} }
......
...@@ -90,7 +90,14 @@ Register GetRegisterThatIsNotOneOf(Register reg1, ...@@ -90,7 +90,14 @@ Register GetRegisterThatIsNotOneOf(Register reg1,
Register reg5 = no_reg, Register reg5 = no_reg,
Register reg6 = no_reg); Register reg6 = no_reg);
bool AreAliased(Register r1, Register r2, Register r3, Register r4); bool AreAliased(Register reg1,
Register reg2,
Register reg3 = no_reg,
Register reg4 = no_reg,
Register reg5 = no_reg,
Register reg6 = no_reg,
Register reg7 = no_reg,
Register reg8 = no_reg);
// ----------------------------------------------------------------------------- // -----------------------------------------------------------------------------
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment