[wasm-simd][x64] Prototype i64x2 widen i32x4

Prototype these 4 instructions:

- i64x2.widen_low_i32x4_s
- i64x2.widen_high_i32x4_s
- i64x2.widen_low_i32x4_u
- i64x2.widen_high_i32x4_u

Bug: v8:10972
Change-Id: I3defd0a2431252bc3f5bb45e022e62b37beb34ca
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2601012
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Reviewed-by: Bill Budge <bbudge@chromium.org>
Cr-Commit-Position: refs/heads/master@{#71888}

src/compiler/backend/instruction-selector.cc

@@ -2751,9 +2751,7 @@ void InstructionSelector::VisitI64x2Eq(Node* node) { UNIMPLEMENTED(); }
 #if !V8_TARGET_ARCH_ARM64 && !V8_TARGET_ARCH_X64
 // TODO(v8:10971) Prototype i16x8.q15mulr_sat_s
 void InstructionSelector::VisitI16x8Q15MulRSatS(Node* node) { UNIMPLEMENTED(); }
-#endif  // !V8_TARGET_ARCH_ARM64 || !V8_TARGET_ARCH_X64
 
-#if !V8_TARGET_ARCH_ARM64
 // TODO(v8:10972) Prototype i64x2 widen i32x4.
 void InstructionSelector::VisitI64x2SConvertI32x4Low(Node* node) {
   UNIMPLEMENTED();
@@ -2770,7 +2768,9 @@ void InstructionSelector::VisitI64x2UConvertI32x4Low(Node* node) {
 void InstructionSelector::VisitI64x2UConvertI32x4High(Node* node) {
   UNIMPLEMENTED();
 }
+#endif  // !V8_TARGET_ARCH_ARM64 || !V8_TARGET_ARCH_X64
 
+#if !V8_TARGET_ARCH_ARM64
 // TODO(v8:11168): Prototyping prefetch.
 void InstructionSelector::VisitPrefetchTemporal(Node* node) { UNIMPLEMENTED(); }
 void InstructionSelector::VisitPrefetchNonTemporal(Node* node) {

src/compiler/backend/x64/code-generator-x64.cc

@@ -2874,6 +2874,39 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
                      /*is_signed=*/false);
       break;
     }
+    case kX64I64x2SConvertI32x4Low: {
+      __ Pmovsxdq(i.OutputSimd128Register(), i.InputSimd128Register(0));
+      break;
+    }
+    case kX64I64x2SConvertI32x4High: {
+      XMMRegister dst = i.OutputSimd128Register();
+      XMMRegister src = i.InputSimd128Register(0);
+      if (CpuFeatures::IsSupported(AVX)) {
+        CpuFeatureScope avx_scope(tasm(), AVX);
+        __ vpunpckhqdq(dst, src, src);
+      } else {
+        __ pshufd(dst, src, 0xEE);
+      }
+      __ Pmovsxdq(dst, dst);
+      break;
+    }
+    case kX64I64x2UConvertI32x4Low: {
+      __ Pmovzxdq(i.OutputSimd128Register(), i.InputSimd128Register(0));
+      break;
+    }
+    case kX64I64x2UConvertI32x4High: {
+      XMMRegister dst = i.OutputSimd128Register();
+      XMMRegister src = i.InputSimd128Register(0);
+      if (CpuFeatures::IsSupported(AVX)) {
+        CpuFeatureScope avx_scope(tasm(), AVX);
+        __ vpxor(kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg);
+        __ vpunpckhdq(dst, src, kScratchDoubleReg);
+      } else {
+        __ pshufd(dst, src, 0xEE);
+        __ pmovzxdq(dst, dst);
+      }
+      break;
+    }
     case kX64I32x4Splat: {
       XMMRegister dst = i.OutputSimd128Register();
       if (HasRegisterInput(instr, 0)) {

src/compiler/backend/x64/instruction-codes-x64.h

@@ -216,6 +216,10 @@ namespace compiler {
   V(X64I64x2ExtMulHighI32x4S)             \
   V(X64I64x2ExtMulLowI32x4U)              \
   V(X64I64x2ExtMulHighI32x4U)             \
+  V(X64I64x2SConvertI32x4Low)             \
+  V(X64I64x2SConvertI32x4High)            \
+  V(X64I64x2UConvertI32x4Low)             \
+  V(X64I64x2UConvertI32x4High)            \
   V(X64I32x4Splat)                        \
   V(X64I32x4ExtractLane)                  \
   V(X64I32x4SConvertF32x4)                \

src/compiler/backend/x64/instruction-scheduler-x64.cc

@@ -192,6 +192,10 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kX64I64x2ExtMulHighI32x4S:
     case kX64I64x2ExtMulLowI32x4U:
     case kX64I64x2ExtMulHighI32x4U:
+    case kX64I64x2SConvertI32x4Low:
+    case kX64I64x2SConvertI32x4High:
+    case kX64I64x2UConvertI32x4Low:
+    case kX64I64x2UConvertI32x4High:
     case kX64I32x4Splat:
     case kX64I32x4ExtractLane:
     case kX64I32x4SConvertF32x4:

src/compiler/backend/x64/instruction-selector-x64.cc

@@ -2911,6 +2911,10 @@ VISIT_ATOMIC_BINOP(Xor)
   V(F32x4RecipSqrtApprox)   \
   V(I64x2Neg)               \
   V(I64x2BitMask)           \
+  V(I64x2SConvertI32x4Low)  \
+  V(I64x2SConvertI32x4High) \
+  V(I64x2UConvertI32x4Low)  \
+  V(I64x2UConvertI32x4High) \
   V(I32x4SConvertI16x8Low)  \
   V(I32x4SConvertI16x8High) \
   V(I32x4Neg)               \

test/cctest/wasm/test-run-wasm-simd.cc

@@ -1812,7 +1812,7 @@ WASM_SIMD_TEST(I32x4ConvertI16x8) {
 
 // TODO(v8:10972) Prototyping i64x2 convert from i32x4.
 // Tests both signed and unsigned conversion from I32x4 (unpacking).
-#if V8_TARGET_ARCH_ARM64
+#if V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_X64
 WASM_SIMD_TEST_NO_LOWERING(I64x2ConvertI32x4) {
   FLAG_SCOPE(wasm_simd_post_mvp);
   WasmRunner<int32_t, int32_t> r(execution_tier, lower_simd);
@@ -1847,7 +1847,7 @@ WASM_SIMD_TEST_NO_LOWERING(I64x2ConvertI32x4) {
     }
   }
 }
-#endif  // V8_TARGET_ARCH_ARM64
+#endif  // V8_TARGET_ARCH_ARM64 || V8_TARGET_ARCH_X64
 
 void RunI32x4UnOpTest(TestExecutionTier execution_tier, LowerSimd lower_simd,
                       WasmOpcode opcode, Int32UnOp expected_op) {