Commit d4385a99 authored by Milad Fa's avatar Milad Fa Committed by V8 LUCI CQ

S390 [liftoff]: Implement simd fp pmin/pmax

Implementations are added to macro-assembler to be shared between
liftoff and code generator.

Change-Id: I3fac2b82686836106cefa9a78f5feda6105679d4
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3412359Reviewed-by: 's avatarJunliang Yan <junyan@redhat.com>
Commit-Queue: Milad Farazmand <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/main@{#78748}
parent c3a1539d
......@@ -5290,6 +5290,8 @@ SIMD_BINOP_LIST_VRR_B(EMIT_SIMD_BINOP_VRR_B)
V(F64x2Min, vfmin, 1, 0, 3) \
V(F64x2Max, vfmax, 1, 0, 3) \
V(F64x2Eq, vfce, 0, 0, 3) \
V(F64x2Pmin, vfmin, 3, 0, 3) \
V(F64x2Pmax, vfmax, 3, 0, 3) \
V(F32x4Add, vfa, 0, 0, 2) \
V(F32x4Sub, vfs, 0, 0, 2) \
V(F32x4Mul, vfm, 0, 0, 2) \
......@@ -5297,6 +5299,8 @@ SIMD_BINOP_LIST_VRR_B(EMIT_SIMD_BINOP_VRR_B)
V(F32x4Min, vfmin, 1, 0, 2) \
V(F32x4Max, vfmax, 1, 0, 2) \
V(F32x4Eq, vfce, 0, 0, 2) \
V(F32x4Pmin, vfmin, 3, 0, 2) \
V(F32x4Pmax, vfmax, 3, 0, 2) \
V(I64x2Add, va, 0, 0, 3) \
V(I64x2Sub, vs, 0, 0, 3) \
V(I32x4Add, va, 0, 0, 2) \
......
......@@ -1148,6 +1148,8 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
V(F64x2Ne, Simd128Register) \
V(F64x2Lt, Simd128Register) \
V(F64x2Le, Simd128Register) \
V(F64x2Pmin, Simd128Register) \
V(F64x2Pmax, Simd128Register) \
V(F32x4Add, Simd128Register) \
V(F32x4Sub, Simd128Register) \
V(F32x4Mul, Simd128Register) \
......@@ -1158,6 +1160,8 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
V(F32x4Ne, Simd128Register) \
V(F32x4Lt, Simd128Register) \
V(F32x4Le, Simd128Register) \
V(F32x4Pmin, Simd128Register) \
V(F32x4Pmax, Simd128Register) \
V(I64x2Add, Simd128Register) \
V(I64x2Sub, Simd128Register) \
V(I64x2Mul, Simd128Register) \
......
......@@ -2565,6 +2565,8 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
V(F64x2Ne, Simd128Register) \
V(F64x2Lt, Simd128Register) \
V(F64x2Le, Simd128Register) \
V(F64x2Pmin, Simd128Register) \
V(F64x2Pmax, Simd128Register) \
V(F32x4Add, Simd128Register) \
V(F32x4Sub, Simd128Register) \
V(F32x4Mul, Simd128Register) \
......@@ -2575,6 +2577,8 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
V(F32x4Ne, Simd128Register) \
V(F32x4Lt, Simd128Register) \
V(F32x4Le, Simd128Register) \
V(F32x4Pmin, Simd128Register) \
V(F32x4Pmax, Simd128Register) \
V(I64x2Add, Simd128Register) \
V(I64x2Sub, Simd128Register) \
V(I64x2Mul, Simd128Register) \
......@@ -3173,30 +3177,6 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
Condition(1));
break;
}
case kS390_F32x4Pmin: {
__ vfmin(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(3), Condition(0),
Condition(2));
break;
}
case kS390_F32x4Pmax: {
__ vfmax(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(3), Condition(0),
Condition(2));
break;
}
case kS390_F64x2Pmin: {
__ vfmin(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(3), Condition(0),
Condition(3));
break;
}
case kS390_F64x2Pmax: {
__ vfmax(i.OutputSimd128Register(), i.InputSimd128Register(0),
i.InputSimd128Register(1), Condition(3), Condition(0),
Condition(3));
break;
}
case kS390_I32x4DotI16x8S: {
Simd128Register tempFPReg1 = i.ToSimd128Register(instr->TempAt(0));
__ vme(kScratchDoubleReg, i.InputSimd128Register(0),
......
......@@ -2276,6 +2276,8 @@ void LiftoffAssembler::emit_smi_check(Register obj, Label* target,
V(f64x2_ne, F64x2Ne, fp) \
V(f64x2_lt, F64x2Lt, fp) \
V(f64x2_le, F64x2Le, fp) \
V(f64x2_pmin, F64x2Pmin, fp) \
V(f64x2_pmax, F64x2Pmax, fp) \
V(f32x4_add, F32x4Add, fp) \
V(f32x4_sub, F32x4Sub, fp) \
V(f32x4_mul, F32x4Mul, fp) \
......@@ -2286,6 +2288,8 @@ void LiftoffAssembler::emit_smi_check(Register obj, Label* target,
V(f32x4_ne, F32x4Ne, fp) \
V(f32x4_lt, F32x4Lt, fp) \
V(f32x4_le, F32x4Le, fp) \
V(f32x4_pmin, F32x4Pmin, fp) \
V(f32x4_pmax, F32x4Pmax, fp) \
V(i64x2_add, I64x2Add, fp) \
V(i64x2_sub, I64x2Sub, fp) \
V(i64x2_mul, I64x2Mul, fp) \
......@@ -2486,16 +2490,6 @@ void LiftoffAssembler::emit_i8x16_swizzle(LiftoffRegister dst,
bailout(kUnsupportedArchitecture, "emit_i8x16_swizzle");
}
void LiftoffAssembler::emit_f64x2_pmin(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kSimd, "pmin unimplemented");
}
void LiftoffAssembler::emit_f64x2_pmax(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kSimd, "pmax unimplemented");
}
void LiftoffAssembler::emit_f64x2_convert_low_i32x4_s(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "f64x2.convert_low_i32x4_s");
......@@ -2511,16 +2505,6 @@ void LiftoffAssembler::emit_f64x2_promote_low_f32x4(LiftoffRegister dst,
bailout(kSimd, "f64x2.promote_low_f32x4");
}
void LiftoffAssembler::emit_f32x4_pmin(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kSimd, "pmin unimplemented");
}
void LiftoffAssembler::emit_f32x4_pmax(LiftoffRegister dst, LiftoffRegister lhs,
LiftoffRegister rhs) {
bailout(kSimd, "pmax unimplemented");
}
void LiftoffAssembler::emit_i64x2_alltrue(LiftoffRegister dst,
LiftoffRegister src) {
bailout(kSimd, "i64x2_alltrue");
......
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