PPC: [wasm-simd] Implement RoundingAverageU operations

Change-Id: I7e7bc48b2e3aa00effec15ae5c8f99adde253fdd
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/2354389
Commit-Queue: Milad Farazmand <miladfar@ca.ibm.com>
Reviewed-by: Junliang Yan <jyan@ca.ibm.com>
Cr-Commit-Position: refs/heads/master@{#69386}

src/codegen/ppc/constants-ppc.h

@@ -2338,7 +2338,11 @@ using Instr = uint32_t;
   /* Vector Add Unsigned Byte Saturate */                  \
   V(vaddubs, VADDUBS, 0x10000200)                          \
   /* Vector Subtract Unsigned Byte Saturate */             \
-  V(vsububs, VSUBUBS, 0x10000600)
+  V(vsububs, VSUBUBS, 0x10000600)                          \
+  /* Vector Average Unsigned Byte */                       \
+  V(vavgub, VAVGUB, 0x10000402)                            \
+  /* Vector Average Unsigned Halfword */                   \
+  V(vavguh, VAVGUH, 0x10000442)
 
 #define PPC_VX_OPCODE_C_FORM_LIST(V)       \
   /* Vector Unpack Low Signed Halfword */  \
@@ -2377,10 +2381,6 @@ using Instr = uint32_t;
   V(vavgsh, VAVGSH, 0x10000542)                                           \
   /* Vector Average Signed Word */                                        \
   V(vavgsw, VAVGSW, 0x10000582)                                           \
-  /* Vector Average Unsigned Byte */                                      \
-  V(vavgub, VAVGUB, 0x10000402)                                           \
-  /* Vector Average Unsigned Halfword */                                  \
-  V(vavguh, VAVGUH, 0x10000442)                                           \
   /* Vector Average Unsigned Word */                                      \
   V(vavguw, VAVGUW, 0x10000482)                                           \
   /* Vector Bit Permute Quadword */                                       \

src/compiler/backend/ppc/code-generator-ppc.cc

@@ -3342,6 +3342,16 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ vor(dst, kScratchDoubleReg, kScratchDoubleReg);
       break;
     }
+    case kPPC_I16x8RoundingAverageU: {
+      __ vavguh(i.OutputSimd128Register(), i.InputSimd128Register(0),
+                i.InputSimd128Register(1));
+      break;
+    }
+    case kPPC_I8x16RoundingAverageU: {
+      __ vavgub(i.OutputSimd128Register(), i.InputSimd128Register(0),
+                i.InputSimd128Register(1));
+      break;
+    }
     case kPPC_StoreCompressTagged: {
       ASSEMBLE_STORE_INTEGER(StoreTaggedField, StoreTaggedFieldX);
       break;

src/compiler/backend/ppc/instruction-codes-ppc.h

@@ -308,6 +308,7 @@ namespace compiler {
   V(PPC_I16x8SubSaturateS)           \
   V(PPC_I16x8AddSaturateU)           \
   V(PPC_I16x8SubSaturateU)           \
+  V(PPC_I16x8RoundingAverageU)       \
   V(PPC_I8x16Splat)                  \
   V(PPC_I8x16ExtractLaneU)           \
   V(PPC_I8x16ExtractLaneS)           \
@@ -336,6 +337,7 @@ namespace compiler {
   V(PPC_I8x16SubSaturateS)           \
   V(PPC_I8x16AddSaturateU)           \
   V(PPC_I8x16SubSaturateU)           \
+  V(PPC_I8x16RoundingAverageU)       \
   V(PPC_S8x16Shuffle)                \
   V(PPC_S8x16Swizzle)                \
   V(PPC_V64x2AnyTrue)                \

src/compiler/backend/ppc/instruction-scheduler-ppc.cc

@@ -231,6 +231,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kPPC_I16x8SubSaturateS:
     case kPPC_I16x8AddSaturateU:
     case kPPC_I16x8SubSaturateU:
+    case kPPC_I16x8RoundingAverageU:
     case kPPC_I8x16Splat:
     case kPPC_I8x16ExtractLaneU:
     case kPPC_I8x16ExtractLaneS:
@@ -259,6 +260,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kPPC_I8x16SubSaturateS:
     case kPPC_I8x16AddSaturateU:
     case kPPC_I8x16SubSaturateU:
+    case kPPC_I8x16RoundingAverageU:
     case kPPC_S8x16Shuffle:
     case kPPC_S8x16Swizzle:
     case kPPC_V64x2AnyTrue:

src/compiler/backend/ppc/instruction-selector-ppc.cc

@@ -2201,6 +2201,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(I16x8SubSaturateS)     \
   V(I16x8AddSaturateU)     \
   V(I16x8SubSaturateU)     \
+  V(I16x8RoundingAverageU) \
   V(I8x16Add)              \
   V(I8x16Sub)              \
   V(I8x16Mul)              \
@@ -2220,6 +2221,7 @@ void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   V(I8x16SubSaturateS)     \
   V(I8x16AddSaturateU)     \
   V(I8x16SubSaturateU)     \
+  V(I8x16RoundingAverageU) \
   V(S128And)               \
   V(S128Or)                \
   V(S128Xor)               \
@@ -2398,14 +2400,6 @@ void InstructionSelector::VisitS128Select(Node* node) {
 
 void InstructionSelector::VisitS128Const(Node* node) { UNIMPLEMENTED(); }
 
-void InstructionSelector::VisitI16x8RoundingAverageU(Node* node) {
-  UNIMPLEMENTED();
-}
-
-void InstructionSelector::VisitI8x16RoundingAverageU(Node* node) {
-  UNIMPLEMENTED();
-}
-
 void InstructionSelector::VisitS128AndNot(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::EmitPrepareResults(