MIPS[64]: Implement MSA 2RF instructions for V8 builtin simulator

Change-Id: Id2eef89f0eba3c59bcdb490e7d986b4b3af0ff9b
Reviewed-on: https://chromium-review.googlesource.com/657677Reviewed-by: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
Commit-Queue: Ivica Bogosavljevic <ivica.bogosavljevic@imgtec.com>
Cr-Commit-Position: refs/heads/master@{#48230}

src/mips/constants-mips.h

@@ -387,6 +387,7 @@ const int kMsaI5Mask = ((7U << 23) | ((1 << 6) - 1));
 const int kMsaMI10Mask = (15U << 2);
 const int kMsaBITMask = ((7U << 23) | ((1 << 6) - 1));
 const int kMsaELMMask = (15U << 22);
+const int kMsaLongerELMMask = kMsaELMMask | (63U << 16);
 const int kMsa3RMask = ((7U << 23) | ((1 << 6) - 1));
 const int kMsa3RFMask = ((15U << 22) | ((1 << 6) - 1));
 const int kMsaVECMask = (23U << 21);
@@ -1602,7 +1603,8 @@ class InstructionGetters : public T {
   }
 
   inline int32_t MsaElmDf() const {
-    DCHECK(this->InstructionType() == InstructionBase::kImmediateType);
+    DCHECK(this->InstructionType() == InstructionBase::kRegisterType ||
+           this->InstructionType() == InstructionBase::kImmediateType);
     int32_t df_n = this->Bits(21, 16);
     if (((df_n >> 4) & 3U) == 0) {
       return 0;
@@ -1618,7 +1620,8 @@ class InstructionGetters : public T {
   }
 
   inline int32_t MsaElmNValue() const {
-    DCHECK(this->InstructionType() == InstructionBase::kImmediateType);
+    DCHECK(this->InstructionType() == InstructionBase::kRegisterType ||
+           this->InstructionType() == InstructionBase::kImmediateType);
     return this->Bits(16 + 4 - this->MsaElmDf(), 16);
   }
 
@@ -1783,6 +1786,15 @@ InstructionBase::Type InstructionBase::InstructionType() const {
         case kMsaMinor2R:
         case kMsaMinor2RF:
           return kRegisterType;
+        case kMsaMinorELM:
+          switch (InstructionBits() & kMsaLongerELMMask) {
+            case CFCMSA:
+            case CTCMSA:
+            case MOVE_V:
+              return kRegisterType;
+            default:
+              return kImmediateType;
+          }
         default:
           return kImmediateType;
       }

src/mips/disasm-mips.cc

@@ -1659,6 +1659,9 @@ void Decoder::DecodeTypeRegister(Instruction* instr) {
         case kMsaMinor2RF:
           DecodeTypeMsa2RF(instr);
           break;
+        case kMsaMinorELM:
+          DecodeTypeMsaELM(instr);
+          break;
         default:
           UNREACHABLE();
       }

src/mips/simulator-mips.h

@@ -257,7 +257,9 @@ class Simulator {
   void set_fcsr_bit(uint32_t cc, bool value);
   bool test_fcsr_bit(uint32_t cc);
   void set_fcsr_rounding_mode(FPURoundingMode mode);
+  void set_msacsr_rounding_mode(FPURoundingMode mode);
   unsigned int get_fcsr_rounding_mode();
+  unsigned int get_msacsr_rounding_mode();
   bool set_fcsr_round_error(double original, double rounded);
   bool set_fcsr_round_error(float original, float rounded);
   bool set_fcsr_round64_error(double original, double rounded);
@@ -266,6 +268,8 @@ class Simulator {
                                int32_t& rounded_int, double fs);
   void round_according_to_fcsr(float toRound, float& rounded,
                                int32_t& rounded_int, float fs);
+  template <typename Tfp, typename Tint>
+  void round_according_to_msacsr(Tfp toRound, Tfp& rounded, Tint& rounded_int);
   void round64_according_to_fcsr(double toRound, double& rounded,
                                  int64_t& rounded_int, double fs);
   void round64_according_to_fcsr(float toRound, float& rounded,
@@ -575,6 +579,8 @@ class Simulator {
   int64_t FPUregisters_[kNumFPURegisters * 2];
   // FPU control register.
   uint32_t FCSR_;
+  // MSA control register.
+  uint32_t MSACSR_;
 
   // Simulator support.
   // Allocate 1MB for stack.

src/mips64/constants-mips64.h

@@ -350,6 +350,7 @@ const int kMsaI5Mask = ((7U << 23) | ((1 << 6) - 1));
 const int kMsaMI10Mask = (15U << 2);
 const int kMsaBITMask = ((7U << 23) | ((1 << 6) - 1));
 const int kMsaELMMask = (15U << 22);
+const int kMsaLongerELMMask = kMsaELMMask | (63U << 16);
 const int kMsa3RMask = ((7U << 23) | ((1 << 6) - 1));
 const int kMsa3RFMask = ((15U << 22) | ((1 << 6) - 1));
 const int kMsaVECMask = (23U << 21);
@@ -1658,7 +1659,8 @@ class InstructionGetters : public T {
   }
 
   inline int32_t MsaElmDf() const {
-    DCHECK(this->InstructionType() == InstructionBase::kImmediateType);
+    DCHECK(this->InstructionType() == InstructionBase::kRegisterType ||
+           this->InstructionType() == InstructionBase::kImmediateType);
     int32_t df_n = this->Bits(21, 16);
     if (((df_n >> 4) & 3U) == 0) {
       return 0;
@@ -1674,7 +1676,8 @@ class InstructionGetters : public T {
   }
 
   inline int32_t MsaElmNValue() const {
-    DCHECK(this->InstructionType() == InstructionBase::kImmediateType);
+    DCHECK(this->InstructionType() == InstructionBase::kRegisterType ||
+           this->InstructionType() == InstructionBase::kImmediateType);
     return this->Bits(16 + 4 - this->MsaElmDf(), 16);
   }
 
@@ -1866,6 +1869,15 @@ InstructionBase::Type InstructionBase::InstructionType() const {
         case kMsaMinor2R:
         case kMsaMinor2RF:
           return kRegisterType;
+        case kMsaMinorELM:
+          switch (InstructionBits() & kMsaLongerELMMask) {
+            case CFCMSA:
+            case CTCMSA:
+            case MOVE_V:
+              return kRegisterType;
+            default:
+              return kImmediateType;
+          }
         default:
           return kImmediateType;
       }

src/mips64/disasm-mips64.cc

@@ -1886,6 +1886,9 @@ int Decoder::DecodeTypeRegister(Instruction* instr) {
         case kMsaMinor2RF:
           DecodeTypeMsa2RF(instr);
           break;
+        case kMsaMinorELM:
+          DecodeTypeMsaELM(instr);
+          break;
         default:
           UNREACHABLE();
       }

src/mips64/simulator-mips64.h

@@ -277,8 +277,13 @@ class Simulator {
                                int32_t& rounded_int, float fs);
   void round64_according_to_fcsr(float toRound, float& rounded,
                                  int64_t& rounded_int, float fs);
+  template <typename T_fp, typename T_int>
+  void round_according_to_msacsr(T_fp toRound, T_fp& rounded,
+                                 T_int& rounded_int);
   void set_fcsr_rounding_mode(FPURoundingMode mode);
+  void set_msacsr_rounding_mode(FPURoundingMode mode);
   unsigned int get_fcsr_rounding_mode();
+  unsigned int get_msacsr_rounding_mode();
   // Special case of set_register and get_register to access the raw PC value.
   void set_pc(int64_t value);
   int64_t get_pc() const;
@@ -602,6 +607,8 @@ class Simulator {
   int64_t FPUregisters_[kNumFPURegisters * 2];
   // FPU control register.
   uint32_t FCSR_;
+  // MSA control register.
+  uint32_t MSACSR_;
 
   // Simulator support.
   // Allocate 1MB for stack.