[V8] Rename SIMD Create methods and add initialization operators.

- Renames Create ops to Splat.
- Adds machine operators to initialize all SIMD machine types.
  Boolean vector types may need initialization, so provide zero
  operators.

LOG=N
BUG=v8:4124,695330

Review-Url: https://codereview.chromium.org/2719483002
Cr-Commit-Position: refs/heads/master@{#43430}

src/compiler/arm/code-generator-arm.cc

@@ -1908,6 +1908,11 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
               i.InputSimd128Register(1));
       break;
     }
+    case kArmSimd128Zero: {
+      __ veor(i.OutputSimd128Register(), i.OutputSimd128Register(),
+              i.OutputSimd128Register());
+      break;
+    }
     case kArmSimd128And: {
       __ vand(i.OutputSimd128Register(), i.InputSimd128Register(0),
               i.InputSimd128Register(1));

src/compiler/arm/instruction-codes-arm.h

@@ -201,6 +201,7 @@ namespace compiler {
   V(ArmUint8x16Max)                \
   V(ArmUint8x16GreaterThan)        \
   V(ArmUint8x16GreaterThanOrEqual) \
+  V(ArmSimd128Zero)                \
   V(ArmSimd128And)                 \
   V(ArmSimd128Or)                  \
   V(ArmSimd128Xor)                 \

src/compiler/arm/instruction-scheduler-arm.cc

@@ -189,6 +189,7 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kArmUint8x16Max:
     case kArmUint8x16GreaterThan:
     case kArmUint8x16GreaterThanOrEqual:
+    case kArmSimd128Zero:
     case kArmSimd128And:
     case kArmSimd128Or:
     case kArmSimd128Xor:

src/compiler/arm/instruction-selector-arm.cc

@@ -2192,6 +2192,12 @@ void InstructionSelector::VisitAtomicStore(Node* node) {
   V(16x8)                   \
   V(8x16)
 
+#define SIMD_ZERO_OP_LIST(V) \
+  V(Simd128Zero)             \
+  V(Simd1x4Zero)             \
+  V(Simd1x8Zero)             \
+  V(Simd1x16Zero)
+
 #define SIMD_UNOP_LIST(V)  \
   V(Float32x4FromInt32x4)  \
   V(Float32x4FromUint32x4) \
@@ -2271,9 +2277,9 @@ void InstructionSelector::VisitAtomicStore(Node* node) {
   V(Int8x16ShiftRightByScalar)  \
   V(Uint8x16ShiftRightByScalar)
 
-#define SIMD_VISIT_SPLAT(Type)                              \
-  void InstructionSelector::VisitCreate##Type(Node* node) { \
-    VisitRR(this, kArm##Type##Splat, node);                 \
+#define SIMD_VISIT_SPLAT(Type)                               \
+  void InstructionSelector::Visit##Type##Splat(Node* node) { \
+    VisitRR(this, kArm##Type##Splat, node);                  \
   }
 SIMD_TYPE_LIST(SIMD_VISIT_SPLAT)
 #undef SIMD_VISIT_SPLAT
@@ -2292,6 +2298,14 @@ SIMD_TYPE_LIST(SIMD_VISIT_EXTRACT_LANE)
 SIMD_TYPE_LIST(SIMD_VISIT_REPLACE_LANE)
 #undef SIMD_VISIT_REPLACE_LANE
 
+#define SIMD_VISIT_ZERO_OP(Name)                                               \
+  void InstructionSelector::Visit##Name(Node* node) {                          \
+    ArmOperandGenerator g(this);                                               \
+    Emit(kArmSimd128Zero, g.DefineAsRegister(node), g.DefineAsRegister(node)); \
+  }
+SIMD_ZERO_OP_LIST(SIMD_VISIT_ZERO_OP)
+#undef SIMD_VISIT_ZERO_OP
+
 #define SIMD_VISIT_UNOP(Name)                         \
   void InstructionSelector::Visit##Name(Node* node) { \
     VisitRR(this, kArm##Name, node);                  \

src/compiler/graph.h

@@ -104,59 +104,6 @@ class V8_EXPORT_PRIVATE Graph final : public NON_EXPORTED_BASE(ZoneObject) {
     Node* nodes[] = {n1, n2, n3, n4, n5, n6, n7, n8, n9};
     return NewNode(op, arraysize(nodes), nodes);
   }
-  Node* NewNode(const Operator* op, Node* n1, Node* n2, Node* n3, Node* n4,
-                Node* n5, Node* n6, Node* n7, Node* n8, Node* n9, Node* n10) {
-    Node* nodes[] = {n1, n2, n3, n4, n5, n6, n7, n8, n9, n10};
-    return NewNode(op, arraysize(nodes), nodes);
-  }
-  Node* NewNode(const Operator* op, Node* n1, Node* n2, Node* n3, Node* n4,
-                Node* n5, Node* n6, Node* n7, Node* n8, Node* n9, Node* n10,
-                Node* n11) {
-    Node* nodes[] = {n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11};
-    return NewNode(op, arraysize(nodes), nodes);
-  }
-  Node* NewNode(const Operator* op, Node* n1, Node* n2, Node* n3, Node* n4,
-                Node* n5, Node* n6, Node* n7, Node* n8, Node* n9, Node* n10,
-                Node* n11, Node* n12) {
-    Node* nodes[] = {n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12};
-    return NewNode(op, arraysize(nodes), nodes);
-  }
-  Node* NewNode(const Operator* op, Node* n1, Node* n2, Node* n3, Node* n4,
-                Node* n5, Node* n6, Node* n7, Node* n8, Node* n9, Node* n10,
-                Node* n11, Node* n12, Node* n13) {
-    Node* nodes[] = {n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13};
-    return NewNode(op, arraysize(nodes), nodes);
-  }
-  Node* NewNode(const Operator* op, Node* n1, Node* n2, Node* n3, Node* n4,
-                Node* n5, Node* n6, Node* n7, Node* n8, Node* n9, Node* n10,
-                Node* n11, Node* n12, Node* n13, Node* n14) {
-    Node* nodes[] = {n1, n2, n3,  n4,  n5,  n6,  n7,
-                     n8, n9, n10, n11, n12, n13, n14};
-    return NewNode(op, arraysize(nodes), nodes);
-  }
-  Node* NewNode(const Operator* op, Node* n1, Node* n2, Node* n3, Node* n4,
-                Node* n5, Node* n6, Node* n7, Node* n8, Node* n9, Node* n10,
-                Node* n11, Node* n12, Node* n13, Node* n14, Node* n15) {
-    Node* nodes[] = {n1, n2,  n3,  n4,  n5,  n6,  n7, n8,
-                     n9, n10, n11, n12, n13, n14, n15};
-    return NewNode(op, arraysize(nodes), nodes);
-  }
-  Node* NewNode(const Operator* op, Node* n1, Node* n2, Node* n3, Node* n4,
-                Node* n5, Node* n6, Node* n7, Node* n8, Node* n9, Node* n10,
-                Node* n11, Node* n12, Node* n13, Node* n14, Node* n15,
-                Node* n16) {
-    Node* nodes[] = {n1, n2,  n3,  n4,  n5,  n6,  n7,  n8,
-                     n9, n10, n11, n12, n13, n14, n15, n16};
-    return NewNode(op, arraysize(nodes), nodes);
-  }
-  Node* NewNode(const Operator* op, Node* n1, Node* n2, Node* n3, Node* n4,
-                Node* n5, Node* n6, Node* n7, Node* n8, Node* n9, Node* n10,
-                Node* n11, Node* n12, Node* n13, Node* n14, Node* n15,
-                Node* n16, Node* n17) {
-    Node* nodes[] = {n1,  n2,  n3,  n4,  n5,  n6,  n7,  n8, n9,
-                     n10, n11, n12, n13, n14, n15, n16, n17};
-    return NewNode(op, arraysize(nodes), nodes);
-  }
 
   // Clone the {node}, and assign a new node id to the copy.
   Node* CloneNode(const Node* node);

src/compiler/instruction-selector.cc

@@ -1457,8 +1457,8 @@ void InstructionSelector::VisitNode(Node* node) {
     case IrOpcode::kUnsafePointerAdd:
       MarkAsRepresentation(MachineType::PointerRepresentation(), node);
       return VisitUnsafePointerAdd(node);
-    case IrOpcode::kCreateFloat32x4:
-      return MarkAsSimd128(node), VisitCreateFloat32x4(node);
+    case IrOpcode::kFloat32x4Splat:
+      return MarkAsSimd128(node), VisitFloat32x4Splat(node);
     case IrOpcode::kFloat32x4ExtractLane:
       return MarkAsFloat32(node), VisitFloat32x4ExtractLane(node);
     case IrOpcode::kFloat32x4ReplaceLane:
@@ -1479,8 +1479,8 @@ void InstructionSelector::VisitNode(Node* node) {
       return MarkAsSimd1x4(node), VisitFloat32x4Equal(node);
     case IrOpcode::kFloat32x4NotEqual:
       return MarkAsSimd1x4(node), VisitFloat32x4NotEqual(node);
-    case IrOpcode::kCreateInt32x4:
-      return MarkAsSimd128(node), VisitCreateInt32x4(node);
+    case IrOpcode::kInt32x4Splat:
+      return MarkAsSimd128(node), VisitInt32x4Splat(node);
     case IrOpcode::kInt32x4ExtractLane:
       return MarkAsWord32(node), VisitInt32x4ExtractLane(node);
     case IrOpcode::kInt32x4ReplaceLane:
@@ -1523,8 +1523,8 @@ void InstructionSelector::VisitNode(Node* node) {
       return MarkAsSimd1x4(node), VisitUint32x4GreaterThan(node);
     case IrOpcode::kUint32x4GreaterThanOrEqual:
       return MarkAsSimd1x4(node), VisitUint32x4GreaterThanOrEqual(node);
-    case IrOpcode::kCreateInt16x8:
-      return MarkAsSimd128(node), VisitCreateInt16x8(node);
+    case IrOpcode::kInt16x8Splat:
+      return MarkAsSimd128(node), VisitInt16x8Splat(node);
     case IrOpcode::kInt16x8ExtractLane:
       return MarkAsWord32(node), VisitInt16x8ExtractLane(node);
     case IrOpcode::kInt16x8ReplaceLane:
@@ -1571,8 +1571,8 @@ void InstructionSelector::VisitNode(Node* node) {
       return MarkAsSimd1x8(node), VisitUint16x8GreaterThan(node);
     case IrOpcode::kUint16x8GreaterThanOrEqual:
       return MarkAsSimd1x8(node), VisitUint16x8GreaterThanOrEqual(node);
-    case IrOpcode::kCreateInt8x16:
-      return MarkAsSimd128(node), VisitCreateInt8x16(node);
+    case IrOpcode::kInt8x16Splat:
+      return MarkAsSimd128(node), VisitInt8x16Splat(node);
     case IrOpcode::kInt8x16ExtractLane:
       return MarkAsWord32(node), VisitInt8x16ExtractLane(node);
     case IrOpcode::kInt8x16ReplaceLane:
@@ -1619,6 +1619,8 @@ void InstructionSelector::VisitNode(Node* node) {
       return MarkAsSimd1x16(node), VisitUint8x16GreaterThan(node);
     case IrOpcode::kUint8x16GreaterThanOrEqual:
       return MarkAsSimd1x16(node), VisitUint16x8GreaterThanOrEqual(node);
+    case IrOpcode::kSimd128Zero:
+      return MarkAsSimd128(node), VisitSimd128Zero(node);
     case IrOpcode::kSimd128And:
       return MarkAsSimd128(node), VisitSimd128And(node);
     case IrOpcode::kSimd128Or:
@@ -1633,6 +1635,12 @@ void InstructionSelector::VisitNode(Node* node) {
       return MarkAsSimd128(node), VisitSimd16x8Select(node);
     case IrOpcode::kSimd8x16Select:
       return MarkAsSimd128(node), VisitSimd8x16Select(node);
+    case IrOpcode::kSimd1x4Zero:
+      return MarkAsSimd1x4(node), VisitSimd1x4Zero(node);
+    case IrOpcode::kSimd1x8Zero:
+      return MarkAsSimd1x8(node), VisitSimd1x8Zero(node);
+    case IrOpcode::kSimd1x16Zero:
+      return MarkAsSimd1x16(node), VisitSimd1x16Zero(node);
     default:
       V8_Fatal(__FILE__, __LINE__, "Unexpected operator #%d:%s @ node #%d",
                node->opcode(), node->op()->mnemonic(), node->id());
@@ -1959,7 +1967,7 @@ void InstructionSelector::VisitWord32PairSar(Node* node) { UNIMPLEMENTED(); }
 #endif  // V8_TARGET_ARCH_64_BIT
 
 #if !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM
-void InstructionSelector::VisitCreateInt32x4(Node* node) { UNIMPLEMENTED(); }
+void InstructionSelector::VisitInt32x4Splat(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitInt32x4ExtractLane(Node* node) {
   UNIMPLEMENTED();
@@ -1973,10 +1981,17 @@ void InstructionSelector::VisitInt32x4Add(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitInt32x4Sub(Node* node) { UNIMPLEMENTED(); }
 
+void InstructionSelector::VisitSimd128Zero(Node* node) { UNIMPLEMENTED(); }
+
+void InstructionSelector::VisitSimd1x4Zero(Node* node) { UNIMPLEMENTED(); }
+
+void InstructionSelector::VisitSimd1x8Zero(Node* node) { UNIMPLEMENTED(); }
+
+void InstructionSelector::VisitSimd1x16Zero(Node* node) { UNIMPLEMENTED(); }
 #endif  // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM
 
 #if !V8_TARGET_ARCH_ARM
-void InstructionSelector::VisitCreateFloat32x4(Node* node) { UNIMPLEMENTED(); }
+void InstructionSelector::VisitFloat32x4Splat(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitFloat32x4ExtractLane(Node* node) {
   UNIMPLEMENTED();
@@ -2066,7 +2081,7 @@ void InstructionSelector::VisitUint32x4GreaterThanOrEqual(Node* node) {
   UNIMPLEMENTED();
 }
 
-void InstructionSelector::VisitCreateInt16x8(Node* node) { UNIMPLEMENTED(); }
+void InstructionSelector::VisitInt16x8Splat(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitInt16x8ExtractLane(Node* node) {
   UNIMPLEMENTED();
@@ -2146,7 +2161,7 @@ void InstructionSelector::VisitUint16x8GreaterThanOrEqual(Node* node) {
   UNIMPLEMENTED();
 }
 
-void InstructionSelector::VisitCreateInt8x16(Node* node) { UNIMPLEMENTED(); }
+void InstructionSelector::VisitInt8x16Splat(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitInt8x16ExtractLane(Node* node) {
   UNIMPLEMENTED();

src/compiler/machine-operator.cc

@@ -220,7 +220,7 @@ MachineRepresentation AtomicStoreRepresentationOf(Operator const* op) {
   V(Word32PairShl, Operator::kNoProperties, 3, 0, 2)                       \
   V(Word32PairShr, Operator::kNoProperties, 3, 0, 2)                       \
   V(Word32PairSar, Operator::kNoProperties, 3, 0, 2)                       \
-  V(CreateFloat32x4, Operator::kNoProperties, 4, 0, 1)                     \
+  V(Float32x4Splat, Operator::kNoProperties, 1, 0, 1)                      \
   V(Float32x4Abs, Operator::kNoProperties, 1, 0, 1)                        \
   V(Float32x4Neg, Operator::kNoProperties, 1, 0, 1)                        \
   V(Float32x4Sqrt, Operator::kNoProperties, 1, 0, 1)                       \
@@ -242,7 +242,7 @@ MachineRepresentation AtomicStoreRepresentationOf(Operator const* op) {
   V(Float32x4GreaterThanOrEqual, Operator::kNoProperties, 2, 0, 1)         \
   V(Float32x4FromInt32x4, Operator::kNoProperties, 1, 0, 1)                \
   V(Float32x4FromUint32x4, Operator::kNoProperties, 1, 0, 1)               \
-  V(CreateInt32x4, Operator::kNoProperties, 4, 0, 1)                       \
+  V(Int32x4Splat, Operator::kNoProperties, 1, 0, 1)                        \
   V(Int32x4Neg, Operator::kNoProperties, 1, 0, 1)                          \
   V(Int32x4Add, Operator::kCommutative, 2, 0, 1)                           \
   V(Int32x4Sub, Operator::kNoProperties, 2, 0, 1)                          \
@@ -269,7 +269,7 @@ MachineRepresentation AtomicStoreRepresentationOf(Operator const* op) {
   V(Bool32x4Not, Operator::kNoProperties, 1, 0, 1)                         \
   V(Bool32x4AnyTrue, Operator::kNoProperties, 1, 0, 1)                     \
   V(Bool32x4AllTrue, Operator::kNoProperties, 1, 0, 1)                     \
-  V(CreateInt16x8, Operator::kNoProperties, 8, 0, 1)                       \
+  V(Int16x8Splat, Operator::kNoProperties, 1, 0, 1)                        \
   V(Int16x8Neg, Operator::kNoProperties, 1, 0, 1)                          \
   V(Int16x8Add, Operator::kCommutative, 2, 0, 1)                           \
   V(Int16x8AddSaturate, Operator::kCommutative, 2, 0, 1)                   \
@@ -298,7 +298,7 @@ MachineRepresentation AtomicStoreRepresentationOf(Operator const* op) {
   V(Bool16x8Not, Operator::kNoProperties, 1, 0, 1)                         \
   V(Bool16x8AnyTrue, Operator::kNoProperties, 1, 0, 1)                     \
   V(Bool16x8AllTrue, Operator::kNoProperties, 1, 0, 1)                     \
-  V(CreateInt8x16, Operator::kNoProperties, 16, 0, 1)                      \
+  V(Int8x16Splat, Operator::kNoProperties, 1, 0, 1)                        \
   V(Int8x16Neg, Operator::kNoProperties, 1, 0, 1)                          \
   V(Int8x16Add, Operator::kCommutative, 2, 0, 1)                           \
   V(Int8x16AddSaturate, Operator::kCommutative, 2, 0, 1)                   \
@@ -335,13 +335,17 @@ MachineRepresentation AtomicStoreRepresentationOf(Operator const* op) {
   V(Simd128Store1, Operator::kNoProperties, 3, 0, 1)                       \
   V(Simd128Store2, Operator::kNoProperties, 3, 0, 1)                       \
   V(Simd128Store3, Operator::kNoProperties, 3, 0, 1)                       \
+  V(Simd128Zero, Operator::kNoProperties, 0, 0, 1)                         \
   V(Simd128And, Operator::kAssociative | Operator::kCommutative, 2, 0, 1)  \
   V(Simd128Or, Operator::kAssociative | Operator::kCommutative, 2, 0, 1)   \
   V(Simd128Xor, Operator::kAssociative | Operator::kCommutative, 2, 0, 1)  \
   V(Simd128Not, Operator::kNoProperties, 1, 0, 1)                          \
   V(Simd32x4Select, Operator::kNoProperties, 3, 0, 1)                      \
   V(Simd16x8Select, Operator::kNoProperties, 3, 0, 1)                      \
-  V(Simd8x16Select, Operator::kNoProperties, 3, 0, 1)
+  V(Simd8x16Select, Operator::kNoProperties, 3, 0, 1)                      \
+  V(Simd1x4Zero, Operator::kNoProperties, 0, 0, 1)                         \
+  V(Simd1x8Zero, Operator::kNoProperties, 0, 0, 1)                         \
+  V(Simd1x16Zero, Operator::kNoProperties, 0, 0, 1)
 
 #define PURE_OPTIONAL_OP_LIST(V)                            \
   V(Word32Ctz, Operator::kNoProperties, 1, 0, 1)            \

src/compiler/machine-operator.h

@@ -425,7 +425,7 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
   const Operator* Float64SilenceNaN();
 
   // SIMD operators.
-  const Operator* CreateFloat32x4();
+  const Operator* Float32x4Splat();
   const Operator* Float32x4ExtractLane(int32_t);
   const Operator* Float32x4ReplaceLane(int32_t);
   const Operator* Float32x4Abs();
@@ -450,7 +450,7 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
   const Operator* Float32x4FromInt32x4();
   const Operator* Float32x4FromUint32x4();
 
-  const Operator* CreateInt32x4();
+  const Operator* Int32x4Splat();
   const Operator* Int32x4ExtractLane(int32_t);
   const Operator* Int32x4ReplaceLane(int32_t);
   const Operator* Int32x4Neg();
@@ -485,7 +485,7 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
   const Operator* Bool32x4AnyTrue();
   const Operator* Bool32x4AllTrue();
 
-  const Operator* CreateInt16x8();
+  const Operator* Int16x8Splat();
   const Operator* Int16x8ExtractLane(int32_t);
   const Operator* Int16x8ReplaceLane(int32_t);
   const Operator* Int16x8Neg();
@@ -522,7 +522,7 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
   const Operator* Bool16x8AnyTrue();
   const Operator* Bool16x8AllTrue();
 
-  const Operator* CreateInt8x16();
+  const Operator* Int8x16Splat();
   const Operator* Int8x16ExtractLane(int32_t);
   const Operator* Int8x16ReplaceLane(int32_t);
   const Operator* Int8x16Neg();
@@ -567,10 +567,13 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
   const Operator* Simd128Store1();
   const Operator* Simd128Store2();
   const Operator* Simd128Store3();
+
+  const Operator* Simd128Zero();
   const Operator* Simd128And();
   const Operator* Simd128Or();
   const Operator* Simd128Xor();
   const Operator* Simd128Not();
+
   const Operator* Simd32x4Select();
   const Operator* Simd32x4Swizzle(uint32_t);
   const Operator* Simd32x4Shuffle();
@@ -581,6 +584,10 @@ class V8_EXPORT_PRIVATE MachineOperatorBuilder final
   const Operator* Simd8x16Swizzle(uint32_t);
   const Operator* Simd8x16Shuffle();
 
+  const Operator* Simd1x4Zero();
+  const Operator* Simd1x8Zero();
+  const Operator* Simd1x16Zero();
+
   // load [base + index]
   const Operator* Load(LoadRepresentation rep);
   const Operator* ProtectedLoad(LoadRepresentation rep);

src/compiler/opcodes.h

@@ -552,7 +552,7 @@
   V(UnsafePointerAdd)
 
 #define MACHINE_SIMD_RETURN_SIMD_OP_LIST(V) \
-  V(CreateFloat32x4)                        \
+  V(Float32x4Splat)                         \
   V(Float32x4ReplaceLane)                   \
   V(Float32x4Abs)                           \
   V(Float32x4Neg)                           \
@@ -575,7 +575,7 @@
   V(Float32x4GreaterThanOrEqual)            \
   V(Float32x4FromInt32x4)                   \
   V(Float32x4FromUint32x4)                  \
-  V(CreateInt32x4)                          \
+  V(Int32x4Splat)                           \
   V(Int32x4ReplaceLane)                     \
   V(Int32x4Neg)                             \
   V(Int32x4Add)                             \
@@ -605,7 +605,7 @@
   V(Bool32x4Or)                             \
   V(Bool32x4Xor)                            \
   V(Bool32x4Not)                            \
-  V(CreateInt16x8)                          \
+  V(Int16x8Splat)                           \
   V(Int16x8ReplaceLane)                     \
   V(Int16x8Neg)                             \
   V(Int16x8Add)                             \
@@ -637,7 +637,7 @@
   V(Bool16x8Or)                             \
   V(Bool16x8Xor)                            \
   V(Bool16x8Not)                            \
-  V(CreateInt8x16)                          \
+  V(Int8x16Splat)                           \
   V(Int8x16ReplaceLane)                     \
   V(Int8x16Neg)                             \
   V(Int8x16Add)                             \
@@ -669,6 +669,7 @@
   V(Bool8x16Or)                             \
   V(Bool8x16Xor)                            \
   V(Bool8x16Not)                            \
+  V(Simd128Zero)                            \
   V(Simd128And)                             \
   V(Simd128Or)                              \
   V(Simd128Xor)                             \
@@ -681,7 +682,10 @@
   V(Simd16x8Shuffle)                        \
   V(Simd8x16Select)                         \
   V(Simd8x16Swizzle)                        \
-  V(Simd8x16Shuffle)
+  V(Simd8x16Shuffle)                        \
+  V(Simd1x4Zero)                            \
+  V(Simd1x8Zero)                            \
+  V(Simd1x16Zero)
 
 #define MACHINE_SIMD_RETURN_NUM_OP_LIST(V) \
   V(Float32x4ExtractLane)                  \

src/compiler/simd-scalar-lowering.cc

@@ -74,13 +74,13 @@ void SimdScalarLowering::LowerGraph() {
 #define FOREACH_INT32X4_OPCODE(V) \
   V(Int32x4Add)                   \
   V(Int32x4ExtractLane)           \
-  V(CreateInt32x4)                \
+  V(Int32x4Splat)                 \
   V(Int32x4ReplaceLane)
 
 #define FOREACH_FLOAT32X4_OPCODE(V) \
   V(Float32x4Add)                   \
   V(Float32x4ExtractLane)           \
-  V(CreateFloat32x4)                \
+  V(Float32x4Splat)                 \
   V(Float32x4ReplaceLane)
 
 void SimdScalarLowering::SetLoweredType(Node* node, Node* output) {
@@ -385,14 +385,14 @@ void SimdScalarLowering::LowerNode(Node* node) {
       LowerBinaryOp(node, rep_type, machine()->Float32Add());
       break;
     }
-    case IrOpcode::kCreateInt32x4:
-    case IrOpcode::kCreateFloat32x4: {
+    case IrOpcode::kInt32x4Splat:
+    case IrOpcode::kFloat32x4Splat: {
       Node* rep_node[kMaxLanes];
       for (int i = 0; i < kMaxLanes; ++i) {
-        if (HasReplacement(0, node->InputAt(i))) {
-          rep_node[i] = GetReplacements(node->InputAt(i))[0];
+        if (HasReplacement(0, node->InputAt(0))) {
+          rep_node[i] = GetReplacements(node->InputAt(0))[0];
         } else {
-          rep_node[i] = node->InputAt(i);
+          rep_node[i] = node->InputAt(0);
         }
       }
       ReplaceNode(node, rep_node);

src/compiler/wasm-compiler.cc

@@ -274,10 +274,16 @@ class WasmTrapHelper : public ZoneObject {
         return jsgraph()->Float32Constant(bit_cast<float>(0xdeadbeef));
       case wasm::kWasmF64:
         return jsgraph()->Float64Constant(bit_cast<double>(0xdeadbeefdeadbeef));
-        break;
+      // We can't always set SIMD types to specific bit patterns. Just zero
+      // them out.
       case wasm::kWasmS128:
-        return builder_->CreateS128Value(0xdeadbeef);
-        break;
+        return builder_->Simd128Zero();
+      case wasm::kWasmS1x4:
+        return builder_->Simd1x4Zero();
+      case wasm::kWasmS1x8:
+        return builder_->Simd1x8Zero();
+      case wasm::kWasmS1x16:
+        return builder_->Simd1x16Zero();
       default:
         UNREACHABLE();
         return nullptr;
@@ -3337,13 +3343,24 @@ void WasmGraphBuilder::SetSourcePosition(Node* node,
     source_position_table_->SetSourcePosition(node, SourcePosition(position));
 }
 
-Node* WasmGraphBuilder::CreateS128Value(int32_t value) {
-  // TODO(gdeepti): Introduce Simd128Constant to common-operator.h and use
-  // instead of creating a SIMD Value.
+Node* WasmGraphBuilder::Simd128Zero() {
+  has_simd_ = true;
+  return graph()->NewNode(jsgraph()->machine()->Simd128Zero());
+}
+
+Node* WasmGraphBuilder::Simd1x4Zero() {
+  has_simd_ = true;
+  return graph()->NewNode(jsgraph()->machine()->Simd1x4Zero());
+}
+
+Node* WasmGraphBuilder::Simd1x8Zero() {
+  has_simd_ = true;
+  return graph()->NewNode(jsgraph()->machine()->Simd1x8Zero());
+}
+
+Node* WasmGraphBuilder::Simd1x16Zero() {
   has_simd_ = true;
-  return graph()->NewNode(jsgraph()->machine()->CreateInt32x4(),
-                          Int32Constant(value), Int32Constant(value),
-                          Int32Constant(value), Int32Constant(value));
+  return graph()->NewNode(jsgraph()->machine()->Simd1x16Zero());
 }
 
 Node* WasmGraphBuilder::SimdOp(wasm::WasmOpcode opcode,
@@ -3351,8 +3368,8 @@ Node* WasmGraphBuilder::SimdOp(wasm::WasmOpcode opcode,
   has_simd_ = true;
   switch (opcode) {
     case wasm::kExprF32x4Splat:
-      return graph()->NewNode(jsgraph()->machine()->CreateFloat32x4(),
-                              inputs[0], inputs[0], inputs[0], inputs[0]);
+      return graph()->NewNode(jsgraph()->machine()->Float32x4Splat(),
+                              inputs[0]);
     case wasm::kExprF32x4SConvertI32x4:
       return graph()->NewNode(jsgraph()->machine()->Float32x4FromInt32x4(),
                               inputs[0]);
@@ -3376,8 +3393,7 @@ Node* WasmGraphBuilder::SimdOp(wasm::WasmOpcode opcode,
       return graph()->NewNode(jsgraph()->machine()->Float32x4NotEqual(),
                               inputs[0], inputs[1]);
     case wasm::kExprI32x4Splat:
-      return graph()->NewNode(jsgraph()->machine()->CreateInt32x4(), inputs[0],
-                              inputs[0], inputs[0], inputs[0]);
+      return graph()->NewNode(jsgraph()->machine()->Int32x4Splat(), inputs[0]);
     case wasm::kExprI32x4SConvertF32x4:
       return graph()->NewNode(jsgraph()->machine()->Int32x4FromFloat32x4(),
                               inputs[0]);
@@ -3440,9 +3456,7 @@ Node* WasmGraphBuilder::SimdOp(wasm::WasmOpcode opcode,
           jsgraph()->machine()->Uint32x4GreaterThanOrEqual(), inputs[0],
           inputs[1]);
     case wasm::kExprI16x8Splat:
-      return graph()->NewNode(jsgraph()->machine()->CreateInt16x8(), inputs[0],
-                              inputs[0], inputs[0], inputs[0], inputs[0],
-                              inputs[0], inputs[0], inputs[0]);
+      return graph()->NewNode(jsgraph()->machine()->Int16x8Splat(), inputs[0]);
     case wasm::kExprI16x8Neg:
       return graph()->NewNode(jsgraph()->machine()->Int16x8Neg(), inputs[0]);
     case wasm::kExprI16x8Add:
@@ -3511,11 +3525,7 @@ Node* WasmGraphBuilder::SimdOp(wasm::WasmOpcode opcode,
           jsgraph()->machine()->Uint16x8GreaterThanOrEqual(), inputs[0],
           inputs[1]);
     case wasm::kExprI8x16Splat:
-      return graph()->NewNode(jsgraph()->machine()->CreateInt8x16(), inputs[0],
-                              inputs[0], inputs[0], inputs[0], inputs[0],
-                              inputs[0], inputs[0], inputs[0], inputs[0],
-                              inputs[0], inputs[0], inputs[0], inputs[0],
-                              inputs[0], inputs[0], inputs[0]);
+      return graph()->NewNode(jsgraph()->machine()->Int8x16Splat(), inputs[0]);
     case wasm::kExprI8x16Neg:
       return graph()->NewNode(jsgraph()->machine()->Int8x16Neg(), inputs[0]);
     case wasm::kExprI8x16Add:

src/compiler/wasm-compiler.h

@@ -228,7 +228,10 @@ class WasmGraphBuilder {
 
   void SetSourcePosition(Node* node, wasm::WasmCodePosition position);
 
-  Node* CreateS128Value(int32_t value);
+  Node* Simd128Zero();
+  Node* Simd1x4Zero();
+  Node* Simd1x8Zero();
+  Node* Simd1x16Zero();
 
   Node* SimdOp(wasm::WasmOpcode opcode, const NodeVector& inputs);
 

src/compiler/x64/code-generator-x64.cc

@@ -2154,7 +2154,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ xchgl(i.InputRegister(index), operand);
       break;
     }
-    case kX64Int32x4Create: {
+    case kX64Int32x4Splat: {
       CpuFeatureScope sse_scope(masm(), SSE4_1);
       XMMRegister dst = i.OutputSimd128Register();
       __ Movd(dst, i.InputRegister(0));
@@ -2186,6 +2186,12 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ psubd(i.OutputSimd128Register(), i.InputSimd128Register(1));
       break;
     }
+    case kX64Simd128Zero: {
+      CpuFeatureScope sse_scope(masm(), SSE4_1);
+      XMMRegister dst = i.OutputSimd128Register();
+      __ xorps(dst, dst);
+      break;
+    }
     case kCheckedLoadInt8:
       ASSEMBLE_CHECKED_LOAD_INTEGER(movsxbl);
       break;

src/compiler/x64/instruction-codes-x64.h

@@ -146,11 +146,12 @@ namespace compiler {
   V(X64Xchgb)                      \
   V(X64Xchgw)                      \
   V(X64Xchgl)                      \
-  V(X64Int32x4Create)              \
+  V(X64Int32x4Splat)               \
   V(X64Int32x4ExtractLane)         \
   V(X64Int32x4ReplaceLane)         \
   V(X64Int32x4Add)                 \
-  V(X64Int32x4Sub)
+  V(X64Int32x4Sub)                 \
+  V(X64Simd128Zero)
 
 // Addressing modes represent the "shape" of inputs to an instruction.
 // Many instructions support multiple addressing modes. Addressing modes

src/compiler/x64/instruction-scheduler-x64.cc

@@ -123,11 +123,12 @@ int InstructionScheduler::GetTargetInstructionFlags(
     case kX64Lea:
     case kX64Dec32:
     case kX64Inc32:
-    case kX64Int32x4Create:
+    case kX64Int32x4Splat:
     case kX64Int32x4ExtractLane:
     case kX64Int32x4ReplaceLane:
     case kX64Int32x4Add:
     case kX64Int32x4Sub:
+    case kX64Simd128Zero:
       return (instr->addressing_mode() == kMode_None)
           ? kNoOpcodeFlags
           : kIsLoadOperation | kHasSideEffect;

src/compiler/x64/instruction-selector-x64.cc

@@ -2274,9 +2274,9 @@ void InstructionSelector::VisitAtomicStore(Node* node) {
   Emit(code, 0, static_cast<InstructionOperand*>(nullptr), input_count, inputs);
 }
 
-void InstructionSelector::VisitCreateInt32x4(Node* node) {
+void InstructionSelector::VisitInt32x4Splat(Node* node) {
   X64OperandGenerator g(this);
-  Emit(kX64Int32x4Create, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
+  Emit(kX64Int32x4Splat, g.DefineAsRegister(node), g.Use(node->InputAt(0)));
 }
 
 void InstructionSelector::VisitInt32x4ExtractLane(Node* node) {
@@ -2306,6 +2306,26 @@ void InstructionSelector::VisitInt32x4Sub(Node* node) {
        g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)));
 }
 
+void InstructionSelector::VisitSimd128Zero(Node* node) {
+  X64OperandGenerator g(this);
+  Emit(kX64Simd128Zero, g.DefineSameAsFirst(node));
+}
+
+void InstructionSelector::VisitSimd1x4Zero(Node* node) {
+  X64OperandGenerator g(this);
+  Emit(kX64Simd128Zero, g.DefineSameAsFirst(node));
+}
+
+void InstructionSelector::VisitSimd1x8Zero(Node* node) {
+  X64OperandGenerator g(this);
+  Emit(kX64Simd128Zero, g.DefineSameAsFirst(node));
+}
+
+void InstructionSelector::VisitSimd1x16Zero(Node* node) {
+  X64OperandGenerator g(this);
+  Emit(kX64Simd128Zero, g.DefineSameAsFirst(node));
+}
+
 // static
 MachineOperatorBuilder::Flags
 InstructionSelector::SupportedMachineOperatorFlags() {

src/wasm/function-body-decoder.cc

@@ -660,7 +660,13 @@ class WasmFullDecoder : public WasmDecoder {
       case kWasmF64:
         return builder_->Float64Constant(0);
       case kWasmS128:
-        return builder_->CreateS128Value(0);
+        return builder_->Simd128Zero();
+      case kWasmS1x4:
+        return builder_->Simd1x4Zero();
+      case kWasmS1x8:
+        return builder_->Simd1x8Zero();
+      case kWasmS1x16:
+        return builder_->Simd1x16Zero();
       default:
         UNREACHABLE();
         return nullptr;