S390[liftoff]: Implement simd load lane ops

Change-Id: I45f3379b3656ee2bc939c97c37d3f15bd730de5a
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/3469177Reviewed-by: Junliang Yan <junyan@redhat.com>
Commit-Queue: Milad Farazmand <mfarazma@redhat.com>
Cr-Commit-Position: refs/heads/main@{#79132}

src/codegen/s390/macro-assembler-s390.cc

@@ -6119,15 +6119,16 @@ void TurboAssembler::LoadV64ZeroLE(Simd128Register dst, const MemOperand& mem) {
   V(16, vlebrh, LoadU16LE, 1) \
   V(8, vleb, LoadU8, 0)
 
-#define LOAD_LANE(name, vector_instr, scalar_instr, condition)               \
-  void TurboAssembler::LoadLane##name##LE(Simd128Register dst,               \
-                                          const MemOperand& mem, int lane) { \
-    if (CAN_LOAD_STORE_REVERSE && is_uint12(mem.offset())) {                 \
-      vector_instr(dst, mem, Condition(lane));                               \
-      return;                                                                \
-    }                                                                        \
-    scalar_instr(r1, mem);                                                   \
-    vlvg(dst, r1, MemOperand(r0, lane), Condition(condition));               \
+#define LOAD_LANE(name, vector_instr, scalar_instr, condition)             \
+  void TurboAssembler::LoadLane##name##LE(Simd128Register dst,             \
+                                          const MemOperand& mem, int lane, \
+                                          Register scratch) {              \
+    if (CAN_LOAD_STORE_REVERSE && is_uint12(mem.offset())) {               \
+      vector_instr(dst, mem, Condition(lane));                             \
+      return;                                                              \
+    }                                                                      \
+    scalar_instr(scratch, mem);                                            \
+    vlvg(dst, scratch, MemOperand(r0, lane), Condition(condition));        \
   }
 LOAD_LANE_LIST(LOAD_LANE)
 #undef LOAD_LANE

src/codegen/s390/macro-assembler-s390.h

@@ -411,10 +411,14 @@ class V8_EXPORT_PRIVATE TurboAssembler : public TurboAssemblerBase {
   void LoadAndExtend32x2SLE(Simd128Register dst, const MemOperand& mem);
   void LoadV32ZeroLE(Simd128Register dst, const MemOperand& mem);
   void LoadV64ZeroLE(Simd128Register dst, const MemOperand& mem);
-  void LoadLane8LE(Simd128Register dst, const MemOperand& mem, int lane);
-  void LoadLane16LE(Simd128Register dst, const MemOperand& mem, int lane);
-  void LoadLane32LE(Simd128Register dst, const MemOperand& mem, int lane);
-  void LoadLane64LE(Simd128Register dst, const MemOperand& mem, int lane);
+  void LoadLane8LE(Simd128Register dst, const MemOperand& mem, int lane,
+                   Register scratch);
+  void LoadLane16LE(Simd128Register dst, const MemOperand& mem, int lane,
+                    Register scratch);
+  void LoadLane32LE(Simd128Register dst, const MemOperand& mem, int lane,
+                    Register scratch);
+  void LoadLane64LE(Simd128Register dst, const MemOperand& mem, int lane,
+                    Register scratch);
   void StoreLane8LE(Simd128Register src, const MemOperand& mem, int lane);
   void StoreLane16LE(Simd128Register src, const MemOperand& mem, int lane);
   void StoreLane32LE(Simd128Register src, const MemOperand& mem, int lane);

src/compiler/backend/s390/code-generator-s390.cc

@@ -3091,7 +3091,7 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
   MemOperand operand = i.MemoryOperand(&mode, &index); \
   Simd128Register dst = i.OutputSimd128Register();     \
   DCHECK_EQ(dst, i.InputSimd128Register(0));           \
-  __ LoadLane##type##LE(dst, operand, lane);
+  __ LoadLane##type##LE(dst, operand, lane, kScratchReg);
     case kS390_S128Load8Lane: {
       LOAD_LANE(8, 15 - i.InputUint8(1));
       break;

src/wasm/baseline/s390/liftoff-assembler-s390.h

@@ -2579,7 +2579,33 @@ void LiftoffAssembler::LoadLane(LiftoffRegister dst, LiftoffRegister src,
                                 Register addr, Register offset_reg,
                                 uintptr_t offset_imm, LoadType type,
                                 uint8_t laneidx, uint32_t* protected_load_pc) {
-  bailout(kSimd, "loadlane");
+  if (!is_int20(offset_imm)) {
+    mov(ip, Operand(offset_imm));
+    if (offset_reg != no_reg) {
+      AddS64(ip, offset_reg);
+    }
+    offset_reg = ip;
+    offset_imm = 0;
+  }
+  MemOperand src_op =
+      MemOperand(addr, offset_reg == no_reg ? r0 : offset_reg, offset_imm);
+
+  MachineType mem_type = type.mem_type();
+  if (dst != src) {
+    vlr(dst.fp(), src.fp(), Condition(0), Condition(0), Condition(0));
+  }
+
+  if (protected_load_pc) *protected_load_pc = pc_offset();
+  if (mem_type == MachineType::Int8()) {
+    LoadLane8LE(dst.fp(), src_op, 15 - laneidx, r1);
+  } else if (mem_type == MachineType::Int16()) {
+    LoadLane16LE(dst.fp(), src_op, 7 - laneidx, r1);
+  } else if (mem_type == MachineType::Int32()) {
+    LoadLane32LE(dst.fp(), src_op, 3 - laneidx, r1);
+  } else {
+    DCHECK_EQ(MachineType::Int64(), mem_type);
+    LoadLane64LE(dst.fp(), src_op, 1 - laneidx, r1);
+  }
 }
 
 void LiftoffAssembler::StoreLane(Register dst, Register offset,