Commit ceb0aef0 authored by Ng Zhi An's avatar Ng Zhi An Committed by Commit Bot

Move some instructions into to sse macro list

Move rcpps, rsqrtps, sqrtps to SSE_INSTRUCTION_LIST.

Bug: v8:9810
Change-Id: Ib95a789dbeb4fc4472da11359cafe76db2027934
Reviewed-on: https://chromium-review.googlesource.com/c/v8/v8/+/1874513Reviewed-by: 's avatarDeepti Gandluri <gdeepti@chromium.org>
Commit-Queue: Zhi An Ng <zhin@chromium.org>
Cr-Commit-Position: refs/heads/master@{#64697}
parent 8b5783dc
......@@ -4003,54 +4003,6 @@ void Assembler::pause() {
emit(0x90);
}
void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x53);
emit_sse_operand(dst, src);
}
void Assembler::rcpps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x53);
emit_sse_operand(dst, src);
}
void Assembler::rsqrtps(XMMRegister dst, XMMRegister src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x52);
emit_sse_operand(dst, src);
}
void Assembler::rsqrtps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x52);
emit_sse_operand(dst, src);
}
void Assembler::sqrtps(XMMRegister dst, XMMRegister src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x51);
emit_sse_operand(dst, src);
}
void Assembler::sqrtps(XMMRegister dst, Operand src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
emit(0x0F);
emit(0x51);
emit_sse_operand(dst, src);
}
void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
EnsureSpace ensure_space(this);
emit_optional_rex_32(dst, src);
......
......@@ -1106,12 +1106,6 @@ class V8_EXPORT_PRIVATE Assembler : public AssemblerBase {
#undef SSE_CMP_P
void rcpps(XMMRegister dst, XMMRegister src);
void rcpps(XMMRegister dst, Operand src);
void rsqrtps(XMMRegister dst, XMMRegister src);
void rsqrtps(XMMRegister dst, Operand src);
void sqrtps(XMMRegister dst, XMMRegister src);
void sqrtps(XMMRegister dst, Operand src);
void movups(XMMRegister dst, XMMRegister src);
void movups(XMMRegister dst, Operand src);
void movups(Operand dst, XMMRegister src);
......
......@@ -6,6 +6,9 @@
#define V8_CODEGEN_X64_SSE_INSTR_H_
#define SSE_INSTRUCTION_LIST(V) \
V(sqrtps, 0F, 51) \
V(rsqrtps, 0F, 52) \
V(rcpps, 0F, 53) \
V(andps, 0F, 54) \
V(andnps, 0F, 55) \
V(orps, 0F, 56) \
......
......@@ -548,10 +548,6 @@ TEST(DisasmX64) {
__ cmpnlepd(xmm5, xmm1);
__ cmpnlepd(xmm5, Operand(rbx, rcx, times_4, 10000));
__ rcpps(xmm5, xmm1);
__ rcpps(xmm5, Operand(rdx, 4));
__ sqrtps(xmm5, xmm1);
__ sqrtps(xmm5, Operand(rdx, 4));
__ movups(xmm5, xmm1);
__ movups(xmm5, Operand(rdx, 4));
__ movups(Operand(rdx, 4), xmm5);
......
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